公开(公告)号：US20060273377A1

公开(公告)日：2006-12-07

申请号：US11504702

申请日：2006-08-16

申请人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

发明人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

IPC分类号： H01L29/788

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7887

摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.

摘要翻译： 提供一种非易失性存储器件及其制造方法。 该器件包括半导体衬底; 设置在所述半导体衬底中的源区和漏区以及置于所述源极和漏极区之间的沟道区; 设置在所述源极区附近的所述沟道区上的第一隧道氧化物层; 设置在漏区附近的沟道区上的第二隧道氧化层; 设置在第一隧道氧化物层上的第一电荷俘获层; 设置在所述第二隧道氧化物层上的第二电荷俘获层; 覆盖第一和第二电荷俘获层的阻挡氧化物层; 介于所述第一和第二电荷俘获层之间的电荷隔离层; 以及设置在阻挡氧化物层上的栅电极。

公开(公告)号：US07112842B2

公开(公告)日：2006-09-26

申请号：US10975996

申请日：2004-10-29

申请人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

发明人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

IPC分类号： H01L29/788 ,  H01L21/338

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7887

摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.

公开(公告)号：US07208365B2

公开(公告)日：2007-04-24

申请号：US11504702

申请日：2006-08-16

申请人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

发明人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

IPC分类号： H01L21/8238

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7887

摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.

摘要翻译： 提供一种非易失性存储器件及其制造方法。 该器件包括半导体衬底; 设置在所述半导体衬底中的源区和漏区以及置于所述源极和漏极区之间的沟道区; 设置在所述源极区附近的所述沟道区上的第一隧道氧化物层; 设置在漏区附近的沟道区上的第二隧道氧化层; 设置在第一隧道氧化物层上的第一电荷俘获层; 设置在所述第二隧道氧化物层上的第二电荷俘获层; 覆盖第一和第二电荷俘获层的阻挡氧化物层; 介于所述第一和第二电荷俘获层之间的电荷隔离层; 以及设置在阻挡氧化物层上的栅电极。

公开(公告)号：US20050162958A1

公开(公告)日：2005-07-28

申请号：US10975996

申请日：2004-10-29

申请人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

发明人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

IPC分类号： H01L21/8247 ,  G11C7/00 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7887

摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.

摘要翻译： 提供一种非易失性存储器件及其制造方法。 该器件包括半导体衬底; 设置在所述半导体衬底中的源区和漏区以及置于所述源极和漏极区之间的沟道区; 设置在所述源极区附近的所述沟道区上的第一隧道氧化物层; 设置在漏区附近的沟道区上的第二隧道氧化层; 设置在第一隧道氧化物层上的第一电荷俘获层; 设置在所述第二隧道氧化物层上的第二电荷俘获层; 覆盖第一和第二电荷俘获层的阻挡氧化物层; 介于所述第一和第二电荷俘获层之间的电荷隔离层; 以及设置在阻挡氧化物层上的栅电极。