公开(公告)号：US09397050B2

公开(公告)日：2016-07-19

申请号：US12551270

申请日：2009-08-31

申请人： HanGil Shin ,  HeeJo Chi ,  NamJu Cho

发明人： HanGil Shin ,  HeeJo Chi ,  NamJu Cho

IPC分类号： H01L21/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/03 ,  H01L23/498

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L2221/68331 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor wafer contains a plurality of semiconductor die. A plurality of bumps is formed on the semiconductor wafer. The bumps are electrically connected to contact pads on an active surface of the die. The bumps can also be pillars or stud bumps. A first encapsulant is deposited over the bumps. The semiconductor wafer is singulated to separate the die by cutting channels partially through the wafer and back grinding the wafer down to the channels. A second encapsulant is deposited over the die. A first interconnect structure is formed over a first surface of the second encapsulant. The first interconnect structure is electrically connected to the bumps. A second interconnect structure is formed over a second surface of the second encapsulant. Secondary semiconductor components can be stacked over the second interconnect structure. A third encapsulant is deposited over the stacked secondary components and second interconnect structure.

摘要翻译： 半导体晶片包含多个半导体管芯。 在半导体晶片上形成多个凸块。 凸块电连接到管芯的有效表面上的接触焊盘。 颠簸也可以是柱子或柱状凸起。 第一密封剂沉积在凸块上。 将半导体晶片单片化以通过部分地通过晶片切割通道并将晶片向下研磨到通道来分离模具。 第二密封剂沉积在模具上。 在第二密封剂的第一表面上形成第一互连结构。 第一互连结构电连接到凸块。 在第二密封剂的第二表面上形成第二互连结构。 次级半导体部件可以堆叠在第二互连结构上。 第三密封剂沉积在堆叠的次级部件和第二互连结构上。

公开(公告)号：US08716065B2

公开(公告)日：2014-05-06

申请号：US13243886

申请日：2011-09-23

申请人： HeeJo Chi ,  NamJu Cho ,  HanGil Shin

发明人： HeeJo Chi ,  NamJu Cho ,  HanGil Shin

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L23/02 ,  H01L23/31 ,  H01L23/16

CPC分类号： H01L23/49811 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05541 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; forming a base encapsulation, having a base encapsulation top side, on the base substrate and around the base integrated circuit; forming a base conductive via, having a base via head, through the base encapsulation and attached to the base substrate adjacent to the base integrated circuit, the base via head exposed from and coplanar with the base encapsulation top side; mounting an interposer structure over the base encapsulation with the interposer structure connected to the base via head; and forming an upper encapsulation on the base encapsulation top side and partially surrounding the interposer structure with a side of the interposer structure facing away from the base encapsulation exposed.

摘要翻译： 一种制造集成电路封装系统的方法，包括：提供基底; 将基底集成电路附接在基底基板上; 在所述基底基板上和所述基底集成电路周围形成具有基底封装顶侧的基底封装; 形成具有基底通孔头部的基底导电通孔，通过基底封装并附接到与基底集成电路相邻的基底基板，基底通孔头部从底部封装顶侧露出并共面; 在基底封装上安装插入器结构，其中插入器结构连接到基底通孔头; 以及在所述基底封装顶侧上形成上部封装并且部分地围绕所述插入件结构，所述插入器结构的侧面背离所述基底封装暴露。

公开(公告)号：US20120319263A1

公开(公告)日：2012-12-20

申请号：US13162513

申请日：2011-06-16

申请人： NamJu Cho ,  HeeJo Chi ,  HanGil Shin

发明人： NamJu Cho ,  HeeJo Chi ,  HanGil Shin

IPC分类号： H01L25/065 ,  H01L21/98

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/18165 ,  H01L2924/19103 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a through hole; mounting an integrated circuit in the through hole, the integrated circuit having an inactive side and a vertical side; connecting a first interconnect in direct contact with the integrated circuit and the substrate; applying a wire-in-film adhesive around and above the integrated circuit leaving a portion of the vertical side and the inactive side exposed and covering a portion of the first interconnect; and mounting a chip above the integrated circuit and in direct contact with the wire-in-film adhesive.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有通孔的基板; 将集成电路安装在通孔中，集成电路具有非活动侧和垂直侧; 连接与集成电路和衬底直接接触的第一互连; 在集成电路周围和上方施加线内胶粘剂，留下垂直侧的一部分和非活动侧暴露并覆盖第一互连的一部分; 并将芯片安装在集成电路上方并与线内胶粘剂直接接触。

公开(公告)号：US20120153467A1

公开(公告)日：2012-06-21

申请号：US13403889

申请日：2012-02-23

申请人： HeeJo Chi ,  NamJu Cho ,  HanGil Shin

发明人： HeeJo Chi ,  NamJu Cho ,  HanGil Shin

IPC分类号： H01L23/498

CPC分类号： H01L21/50 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/19 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012

摘要： A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die.

公开(公告)号：US20110215448A1

公开(公告)日：2011-09-08

申请号：US12716269

申请日：2010-03-02

申请人： NamJu Cho ,  HeeJo Chi ,  HanGil Shin

发明人： NamJu Cho ,  HeeJo Chi ,  HanGil Shin

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/495 ,  H01L23/552 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit package system includes: providing a base package substrate including: forming component contacts on a component side of the base package substrate, forming system contacts on a system side of the base package substrate, and forming a reference voltage circuit between the component contacts and the system contacts; mounting a first integrated circuit die on the component contacts; mounting a lead frame on the first integrated circuit die and coupled to the component contacts; and isolating a conductive shield from the lead frame, the conductive shield coupled to the reference voltage circuit.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供基底封装基板，包括：在所述基底封装基板的元件侧上形成元件触点，在所述基底封装基板的系统侧形成系统触点，以及形成基准电压 组件触点和系统触点之间的电路; 在组件触点上安装第一集成电路管芯; 将引线框架安装在第一集成电路管芯上并耦合到部件触点; 并且将导电屏蔽与引线框架隔离，所述导电屏蔽件耦合到参考电压电路。

公开(公告)号：US20110140259A1

公开(公告)日：2011-06-16

申请号：US12639984

申请日：2009-12-16

申请人： NamJu Cho ,  HeeJo Chi ,  HanGil Shin ,  Rui Huang ,  Seng Guan Chow ,  Heap Hoe Kuan

发明人： NamJu Cho ,  HeeJo Chi ,  HanGil Shin ,  Rui Huang ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L23/52 ,  H01L21/98 ,  H01L25/065

CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate; coupling a conductive column lead frame to the base package substrate by: providing a lead frame support, patterning a conductive material on the lead frame support including forming an interconnect securing structure, and coupling the conductive material to the base package substrate; forming a base package body between the base package substrate and the conductive column lead frame; and removing the lead frame support from the conductive column lead frame for exposing the interconnect securing structure from the base package body.

摘要翻译： 一种集成电路封装系统的制造方法，包括：制造基底封装基板; 通过以下方式将导电柱引线框架耦合到基底封装基板：提供引线框架支撑件，在引线框架支架上图形化导电材料，包括形成互连固定结构，以及将导电材料耦合到基底封装基板; 在所述基底封装基板和所述导电柱引线框架之间形成基底封装体; 以及从所述导电柱引线框架移除所述引线框支撑件，用于将所述互连固定结构从所述基底封装主体露出。

公开(公告)号：US07928552B1

公开(公告)日：2011-04-19

申请号：US12722759

申请日：2010-03-12

申请人： NamJu Cho ,  HeeJo Chi ,  HanGil Shin

发明人： NamJu Cho ,  HeeJo Chi ,  HanGil Shin

IPC分类号： H01L23/522

CPC分类号： H01L23/49827 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/16 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a carrier having a planar surface and a cavity therein, a first barrier between the planar surface and a first interconnect, and a second barrier between the cavity and a second interconnect; providing a substrate; mounting an integrated circuit over the substrate; mounting the carrier to the substrate with the first interconnect and the second interconnect attached to the substrate and with the planar surface over the integrated circuit; forming an encapsulation between the substrate and the carrier covering the integrated circuit, the encapsulation having an encapsulation recess under the planar surface and over the integrated circuit; and removing a portion of the carrier to expose the encapsulation, a portion of the first barrier to form a first contact pad, and a portion of the second barrier to form a second contact pad.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有平坦表面和其中的空腔的载体，平面和第一互连之间的第一屏障，以及在所述空腔和第二互连之间的第二屏障; 提供衬底; 在基板上安装集成电路; 将所述载体安装到所述基板上，所述第一互连件和所述第二互连件附接到所述基板并且所述平面表面在所述集成电路上; 在衬底和覆盖集成电路的载体之间形成封装，该封装在平坦表面下方和集成电路之下具有封装凹槽; 以及去除所述载体的一部分以暴露所述封装，所述第一屏障的一部分以形成第一接触焊盘，以及所述第二屏障的一部分以形成第二接触焊盘。

公开(公告)号：US20110068453A1

公开(公告)日：2011-03-24

申请号：US12563514

申请日：2009-09-21

申请人： NamJu Cho ,  HeeJo Chi ,  HanGil Shin

发明人： NamJu Cho ,  HeeJo Chi ,  HanGil Shin

IPC分类号： H01L23/52 ,  H01L21/56 ,  H01L21/60

CPC分类号： H01L23/49811 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; attaching a buffer interconnect to and over the substrate; forming an encapsulation over the substrate covering the buffer interconnect and the integrated circuit; and forming a via in the encapsulation and to the buffer interconnect.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供基板; 在基板上安装集成电路; 将缓冲器互连件附接到所述基板上方和上方; 在覆盖缓冲器互连和集成电路的衬底上形成封装; 以及在封装和缓冲互连中形成通孔。

公开(公告)号：US20110049695A1

公开(公告)日：2011-03-03

申请号：US12551270

申请日：2009-08-31

申请人： HanGil Shin ,  HeeJo Chi ,  NamJu Cho

发明人： HanGil Shin ,  HeeJo Chi ,  NamJu Cho

IPC分类号： H01L23/52 ,  H01L21/50

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L2221/68331 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor wafer contains a plurality of semiconductor die. A plurality of bumps is formed on the semiconductor wafer. The bumps are electrically connected to contact pads on an active surface of the die. The bumps can also be pillars or stud bumps. A first encapsulant is deposited over the bumps. The semiconductor wafer is singulated to separate the die by cutting channels partially through the wafer and back grinding the wafer down to the channels. A second encapsulant is deposited over the die. A first interconnect structure is formed over a first surface of the second encapsulant. The first interconnect structure is electrically connected to the bumps. A second interconnect structure is formed over a second surface of the second encapsulant. Secondary semiconductor components can be stacked over the second interconnect structure. A third encapsulant is deposited over the stacked secondary components and second interconnect structure.

摘要翻译： 半导体晶片包含多个半导体管芯。 在半导体晶片上形成多个凸块。 凸块电连接到管芯的有效表面上的接触焊盘。 颠簸也可以是柱子或柱状凸起。 第一密封剂沉积在凸块上。 将半导体晶片单片化以通过部分地通过晶片切割通道并将晶片向下研磨到通道来分离模具。 第二密封剂沉积在模具上。 在第二密封剂的第一表面上形成第一互连结构。 第一互连结构电连接到凸块。 在第二密封剂的第二表面上形成第二互连结构。 次级半导体部件可以堆叠在第二互连结构上。 第三密封剂沉积在堆叠的次级部件和第二互连结构上。

公开(公告)号：US09269595B2

公开(公告)日：2016-02-23

申请号：US13403859

申请日：2012-02-23

申请人： HeeJo Chi ,  NamJu Cho ,  HanGil Shin

发明人： HeeJo Chi ,  NamJu Cho ,  HanGil Shin

IPC分类号： H01L21/44 ,  H01L21/50 ,  H01L21/78 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L21/50 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/19 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012

摘要： A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die.

摘要翻译： 半导体晶片具有多个第一半导体管芯。 第二半导体管芯安装到第一半导体管芯。 第一半导体管芯的有源表面朝向第二半导体管芯的有源表面。 密封剂沉积在第一和第二半导体管芯上。 第二半导体管芯的与有源表面相对的后表面的一部分被去除。 在第二半导体管芯周围形成导电柱。 TSV可以通过第一半导体管芯形成。 在第二半导体管芯，密封剂和导电柱的后表面上形成互连结构。 互连结构电连接到导电柱。 去除与活性表面相对的第一半导体管芯的后表面的一部分。 可以在第一半导体管芯的后表面上形成散热器或屏蔽层。