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    Fall time accelerator circuit
    1.
    发明授权
    Fall time accelerator circuit 有权
    下降时间加速器电路

    公开(公告)号：US07992030B2

    公开(公告)日：2011-08-02

    申请号：US11746102

    申请日：2007-05-09

    申请人： Henry G. McMillan ,  Pravin Patel ,  Challis L. Purrington ,  Gwendolyn R. Tobin ,  Christopher C. West ,  Ivan R. Zapata

    发明人： Henry G. McMillan ,  Pravin Patel ,  Challis L. Purrington ,  Gwendolyn R. Tobin ,  Christopher C. West ,  Ivan R. Zapata

    IPC分类号： G06F1/00

    CPC分类号： H03K5/1534 ,  H03K19/01721

    摘要： Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus.

    摘要翻译： 本发明的实施例解决了与数字信号传输相关的技术缺陷，并且提供了一种用于USB接口的新颖且不可见的下降时间加速器电路。 在本发明的一个实施例中，USB接口可以包括通过USB总线耦合到主控制器驱动器的USB端口驱动器。 USB接口还可以包括在USB端口驱动器和主机控制器驱动器之间耦合到USB总线的下降时间加速器电路。 下降时间加速器电路可以包括耦合到来自USB总线的入站信号路径的脉冲信号发生器，并且被布置成在检测入站信号路径上的数字信号的下降沿时产生可调脉冲。 电路还可以包括另外耦合到入站信号路径的有源定时器，以将可调谐脉冲保持一段时间。 最后，电路可以包括耦合到来自脉冲信号发生器的出站信号路径的下降驱动信号加强器，该脉冲信号发生器布置成将出站信号路径上的可调谐脉冲释放到USB总线上。

    FALL TIME ACCELERATOR CIRCUIT
    2.
    发明申请
    FALL TIME ACCELERATOR CIRCUIT 有权
    落地时间加速器电路

    公开(公告)号：US20080278207A1

    公开(公告)日：2008-11-13

    申请号：US11746102

    申请日：2007-05-09

    申请人： Henry G. McMillan ,  Pravin Patel ,  Challis L. Purrington ,  Gwendolyn R. Tobin ,  Christopher C. West ,  Ivan R. Zapata

    发明人： Henry G. McMillan ,  Pravin Patel ,  Challis L. Purrington ,  Gwendolyn R. Tobin ,  Christopher C. West ,  Ivan R. Zapata

    IPC分类号： H03K5/12

    CPC分类号： H03K5/1534 ,  H03K19/01721

    摘要： Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus.

    摘要翻译： 本发明的实施例解决了与数字信号传输相关的技术缺陷，并且提供了一种用于USB接口的新颖且不可见的下降时间加速器电路。 在本发明的一个实施例中，USB接口可以包括通过USB总线耦合到主控制器驱动器的USB端口驱动器。 USB接口还可以包括在USB端口驱动器和主机控制器驱动器之间耦合到USB总线的下降时间加速器电路。 下降时间加速器电路可以包括耦合到来自USB总线的入站信号路径的脉冲信号发生器，并且被布置成在检测入站信号路径上的数字信号的下降沿时产生可调脉冲。 电路还可以包括另外耦合到入站信号路径的有源定时器，以将可调谐脉冲保持一段时间。 最后，电路可以包括耦合到来自脉冲信号发生器的出站信号路径的下降驱动信号加强器，该脉冲信号发生器布置成将出站信号路径上的可调谐脉冲释放到USB总线上。

    Optimizing A Physical Data Communications Topology Between A Plurality Of Computing Nodes
    7.
    发明申请
    Optimizing A Physical Data Communications Topology Between A Plurality Of Computing Nodes 有权
    优化多个计算节点之间的物理数据通信拓扑

    公开(公告)号：US20090219835A1

    公开(公告)日：2009-09-03

    申请号：US12040316

    申请日：2008-02-29

    申请人： Justin P. Bandholz ,  Zachary B. Durham ,  Clifton E. Kerr ,  Joseph E. Maxwell ,  Kevin M. Reinberg ,  Kevin S. Vernon ,  Philip L. Weinstein ,  Christopher C. West

    发明人： Justin P. Bandholz ,  Zachary B. Durham ,  Clifton E. Kerr ,  Joseph E. Maxwell ,  Kevin M. Reinberg ,  Kevin S. Vernon ,  Philip L. Weinstein ,  Christopher C. West

    IPC分类号： H04L12/28

    CPC分类号： H04L41/0823 ,  H04L12/462 ,  H04L41/08 ,  H04L41/085 ,  H04L41/12 ,  H04L47/10

    摘要： Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights.

    摘要翻译： 公开了用于优化多个计算节点之间的物理数据通信拓扑的方法，装置和产品，所述物理数据通信拓扑包括被配置为连接用于数据通信的多个节点的物理链路，其包括以预定速度反复进行 ：通过物理数据通信拓扑中的每对节点之间的链路检测网络数据包，每个网络分组的特征在于一个或多个分组属性; 根据该网络分组的分组属性向每个网络分组分配分组权重; 根据分配给在该对节点之间传送的网络分组的分组权重，为物理数据通信拓扑中的每对节点确定节点对业务权重; 并且根据节点对业务权重重新配置每对节点之间的物理链路。