公开(公告)号：US5844914A

公开(公告)日：1998-12-01

申请号：US850807

申请日：1997-05-02

申请人： Heon-Cheol Kim ,  Hong-Sin Jun ,  Chang-Hyun Cho

发明人： Heon-Cheol Kim ,  Hong-Sin Jun ,  Chang-Hyun Cho

IPC分类号： G11C11/401 ,  G01R31/28 ,  G01R31/3181 ,  G11C11/406 ,  G11C29/08 ,  G11C29/12 ,  G11C29/18 ,  G06F11/00

CPC分类号： G11C29/18 ,  G01R31/31813

摘要： A semiconductor memory device and method is shown in which a built-in system test (BIST) circuit determines, based upon the test algorithm and the refresh requirements of a DRAM memory cell array, a refresh point address where the BIST circuit performs a refresh operation on the test data in the memory cell array when the test address reaches the refresh point address. Another embodiment of a semiconductor memory device and method is also shown in which a BIST circuit descrambles the test address and test data before input to a memory circuit which includes address and data scrambling circuits such that the logical test address and test data generated according to a test algorithm matches the physical address and data in the memory cell array.

摘要翻译： 示出了半导体存储器件和方法，其中内置系统测试（BIST）电路基于测试算法和DRAM存储单元阵列的刷新要求确定BIST电路执行刷新操作的刷新点地址 当测试地址到达刷新点地址时，在存储单元阵列中的测试数据。 还示出了半导体存储器件和方法的另一实施例，其中BIST电路在输入到存储器电路之前对测试地址和测试数据进行解扰，该存储器电路包括地址和数据加扰电路，使得逻辑测试地址和根据 测试算法与存储单元阵列中的物理地址和数据相匹配。

公开(公告)号：US5938784A

公开(公告)日：1999-08-17

申请号：US951189

申请日：1997-10-15

申请人： Heon-Cheol Kim

发明人： Heon-Cheol Kim

IPC分类号： G06F7/00 ,  G01R3/00 ,  G01R31/3181 ,  G06F11/22 ,  G11C19/00 ,  G11C29/00 ,  G11C29/12 ,  G01R31/28

CPC分类号： G01R31/31813

摘要： A built-in self test (BIST) circuit using a linear feedback shift register (LFSR) and a multiple input signature register (MISR) requiring reduced circuitry exclusive of the number of inputs and outputs of the circuit to be tested. The BIST circuit is built in a prescribed circuit having a memory to test a target circuit in the prescribed circuit. The BIST circuit includes an LFSR, including a first logic section which is composed of a plurality of XOR gates and selection sections, and a first memory which is a part of the memory, for performing a primitive polynomial, an MISR, including a second logic section which is composed of a plurality of XOR gates and selection sections, and a second memory which is a part of the memory, for performing the primitive polynomial, and a BIST control section for controlling data input/output between the first and second memories and the target circuit and providing selection signals for controlling the selection sections in the first and second logic sections, the BIST control section controlling the target circuit and comparing operation results of the target circuit to perform the test of the target circuit.

摘要翻译： 使用线性反馈移位寄存器（LFSR）和多输入签名寄存器（MISR）的内置自检（BIST）电路，需要减少电路，不包括待测电路的输入和输出数量。 BIST电路内置在具有用于测试规定电路中的目标电路的存储器的规定电路中。 BIST电路包括LFSR，其包括由多个XOR门和选择部分组成的第一逻辑部分和作为存储器的一部分的第一存储器，用于执行原始多项式，MISR包括第二逻辑 由多个XOR门和选择部分组成的部分，以及作为存储器的一部分的第二存储器，用于执行原始多项式;以及BIST控制部分，用于控制第一和第二存储器之间的数据输入/输出; 目标电路并提供用于控制第一和第二逻辑部分中的选择部分的选择信号，BIST控制部分控制目标电路并比较目标电路的运行结果以执行目标电路的测试。

公开(公告)号：US06574757B1

公开(公告)日：2003-06-03

申请号：US09566346

申请日：2000-05-08

申请人： Jin-Young Park ,  Heon-Cheol Kim

发明人： Jin-Young Park ,  Heon-Cheol Kim

IPC分类号： G11C2900

CPC分类号： G11C29/72 ,  G11C29/44 ,  G11C29/4401

摘要： An integrated circuit semiconductor device comprises a built-in self-repair (BISR) circuit including a plurality of row fill entries and a plurality of column fill entries for storing faulty memory cell information of an embedded memory. Sizes of the row and column fill entries are determined by the numbers of row and column redundancies of the embedded memory. The row/column fill entries store row/column addresses of the faulty memory cells, and the number of the faulty memory cells occurring at the same row/column address, respectively. In addition, the row/column fill entries include pointers for indicating opposite entries storing the column/row address corresponding to the row/column address. For repairing the faulty memory cells with the row and column redundancies, the BISR circuit selects row/column fill entries and deletes the number of the fault memory cells stored in the opposite fill entry. Thus, the information is deleted from the row/column fill entries with the exception of information to be repaired. Therefore, the self-repair of the faulty memory cells can be performed in the BISR circuit in response to the remaining information.

摘要翻译： 集成电路半导体器件包括内置的自修复（BISR）电路，其包括多个行填充条目和用于存储嵌入式存储器的有缺陷的存储器单元信息的多个列填充条目。 行和列填充条目的大小由嵌入式存储器的行和列冗余数决定。 行/列填充条目分别存储故障存储器单元的行/列地址以及在相同行/列地址处发生的故障存储器单元的数量。 此外，行/列填充条目包括用于指示存储与行/列地址相对应的列/行地址的相反条目的指针。 为了修复具有行和列冗余的故障存储单元，BISR电路选择行/列填充条目，并删除存储在相反填充条目中的故障存储单元的数量。 因此，除了要修复的信息之外，信息将从行/列填充条目中删除。 因此，可以在BISR电路中响应于剩余的信息来执行故障存储器单元的自修复。