公开(公告)号：US07193262B2

公开(公告)日：2007-03-20

申请号：US10905094

申请日：2004-12-15

申请人： Herbert L. Ho ,  John E. Barth, Jr. ,  Ramachandra Divakaruni ,  Wayne F. Ellis ,  Johnathan E. Faltermeier ,  Brent A. Anderson ,  Subramanian S. Iyer ,  Deok-Kee Kim ,  Randy W. Mann ,  Paul C. Parries

发明人： Herbert L. Ho ,  John E. Barth, Jr. ,  Ramachandra Divakaruni ,  Wayne F. Ellis ,  Johnathan E. Faltermeier ,  Brent A. Anderson ,  Subramanian S. Iyer ,  Deok-Kee Kim ,  Randy W. Mann ,  Paul C. Parries

IPC分类号： H01L29/94 ,  H01L29/00

CPC分类号： H01L27/0805 ,  H01L29/66181 ,  H01L29/945

摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.

摘要翻译： 一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。 在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

公开(公告)号：US06429101B1

公开(公告)日：2002-08-06

申请号：US09240753

申请日：1999-01-29

申请人： Ricky S. Amos ,  Arne W. Ballantine ,  Gregory Bazan ,  Bomy A. Chen ,  Douglas D. Coolbaugh ,  Ramachandra Divakaruni ,  Heidi L. Greer ,  Herbert L. Ho ,  Joseph F. Kudlacik ,  Bernard P. Leroy ,  Paul C. Parries ,  Gary L. Patton

发明人： Ricky S. Amos ,  Arne W. Ballantine ,  Gregory Bazan ,  Bomy A. Chen ,  Douglas D. Coolbaugh ,  Ramachandra Divakaruni ,  Heidi L. Greer ,  Herbert L. Ho ,  Joseph F. Kudlacik ,  Bernard P. Leroy ,  Paul C. Parries ,  Gary L. Patton

IPC分类号： H01L2120

CPC分类号： H01L21/02126 ,  H01L21/0214 ,  H01L21/02236 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/31662

摘要： A method for forming a thermally stable ohmic contact structure that includes a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of dielectric material is formed between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.

摘要翻译： 一种形成包含单晶半导体区域和多晶半导体区域的热稳定欧姆接触结构的方法。 在单晶半导体区域的至少一部分与多晶半导体区域之间形成介电材料的至少一个区域，从而控制多晶半导体的晶粒生长。

公开(公告)号：US06518641B2

公开(公告)日：2003-02-11

申请号：US09861274

申请日：2001-05-18

申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Johnathan E. Faltermeier ,  William R. Tonti

发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Johnathan E. Faltermeier ,  William R. Tonti

IPC分类号： H01L2900

CPC分类号： H01L21/76232 ,  H01L21/764

摘要： An isolation region for a memory array in which the isolation region includes at least one trench region having sidewalls that extend to a bottom surface and a slit region formed beneath the final trench region, wherein the slit region is narrower than the overlying trench regions and has a void formed intentionally therein is provided.

摘要翻译： 一种用于存储器阵列的隔离区域，其中隔离区域包括至少一个具有延伸到底表面的侧壁和形成在最终沟槽区域下方的狭缝区域的沟槽区域，其中狭缝区域比上覆沟槽区域窄，并且具有 提供了有意形成的空隙。

公开(公告)号：US06686668B2

公开(公告)日：2004-02-03

申请号：US09764833

申请日：2001-01-17

申请人： Larry A. Nesbit ,  Johnathan E. Faltermeier ,  Ramachandra Divakaruni ,  Wolfgang Bergner

发明人： Larry A. Nesbit ,  Johnathan E. Faltermeier ,  Ramachandra Divakaruni ,  Wolfgang Bergner

IPC分类号： H01L27108

CPC分类号： H01L27/10885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10888

摘要： A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed over portions of the oxide layer. The bitline contact mask is etched, and a silicon layer is deposited on the substrate. A bitline layer is deposited on the silicon layer. A masking and etching operation is performed on the bitline layer. A M0 metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M0) layer to form left and right bitlines.

公开(公告)号：US20080261128A1

公开(公告)日：2008-10-23

申请号：US12106586

申请日：2008-04-21

申请人： Deok-kee Kim ,  Kenneth T. Settlemyer ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Thimothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

发明人： Deok-kee Kim ,  Kenneth T. Settlemyer ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Thimothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

IPC分类号： G03F7/004 ,  G03F7/20

CPC分类号： H01L21/0337 ,  G03F7/11 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0338 ,  H01L21/31144

摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

摘要翻译： 增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。 提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。 这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

公开(公告)号：US07195972B2

公开(公告)日：2007-03-27

申请号：US10886439

申请日：2004-07-06

申请人： Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Deok-kee Kim

发明人： Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Deok-kee Kim

IPC分类号： H01L21/8242

CPC分类号： H01L27/10891 ,  H01L27/10864 ,  H01L27/1203

摘要： A trench capacitor DRAM cell in an SOI wafer uses the silicon device layer in the array as part of passing wordlines, stripping the silicon device layer in the array outside the wordlines and uses the BOX layer as the array top oxide separating the passing wordlines from the substrate.

摘要翻译： SOI晶片中的沟槽电容器DRAM单元使用阵列中的硅器件层作为通过字线的一部分，剥离字线外的阵列中的硅器件层，并使用BOX层作为阵列顶部氧化物，将通过的字线与 基质。

公开(公告)号：US20050255386A1

公开(公告)日：2005-11-17

申请号：US10709514

申请日：2004-05-11

申请人： Deok-kee Kim ,  Kenneth Settlemyer ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens ,  Dirk Pfeiffer ,  Timothy Dalton ,  Katherina Babich ,  Arpan Mahorowala ,  Harald Okorn-Schmidt

发明人： Deok-kee Kim ,  Kenneth Settlemyer ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens ,  Dirk Pfeiffer ,  Timothy Dalton ,  Katherina Babich ,  Arpan Mahorowala ,  Harald Okorn-Schmidt

IPC分类号： G03C5/00 ,  G03F7/11 ,  G03F9/00 ,  H01L21/033 ,  H01L21/311 ,  H01L21/331

CPC分类号： H01L21/0337 ,  G03F7/11 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0338 ,  H01L21/31144

摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

摘要翻译： 增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。 提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。 这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

公开(公告)号：US07601646B2

公开(公告)日：2009-10-13

申请号：US10710566

申请日：2004-07-21

申请人： Deok-kee Kim ,  Ramachandra Divakaruni ,  Hiroyuki Akatsu ,  George Worth ,  Jay Strane ,  Byeong Kim

发明人： Deok-kee Kim ,  Ramachandra Divakaruni ,  Hiroyuki Akatsu ,  George Worth ,  Jay Strane ,  Byeong Kim

IPC分类号： H01L21/3065 ,  H01L21/308 ,  H01L21/311

CPC分类号： H01L27/10894 ,  H01L21/31053 ,  H01L27/10841 ,  H01L27/10897

摘要： Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.

摘要翻译： 通过减少各个差异化区域中的结构之间的高度/台阶高差，可以提高具有差异化区域（例如存储器的阵列和支撑区域）的集成电路的制造产量，并且与顶部氧化物早期（TOE）和顶部 氧化物晚期过程。 新颖的平面化技术避免了由于刮擦，碎裂或凹陷而导致的有源器件，隔离结构等的损坏，这对于使用TON工艺提高制造产量特别有效，并且当平均高度/台阶高度基本相等时也使用TOE和TOL工艺。 还可以使用诸如多晶硅的替代掩模材料来简化和/或改进工艺的控制。

公开(公告)号：US20060226481A1

公开(公告)日：2006-10-12

申请号：US10907630

申请日：2005-04-08

申请人： Deok-kee Kim ,  Ramachandra Divakaruni ,  Carl Radens ,  Dae-Gyu Park

发明人： Deok-kee Kim ,  Ramachandra Divakaruni ,  Carl Radens ,  Dae-Gyu Park

IPC分类号： H01L27/12

CPC分类号： H01L27/12 ,  H01L27/10841 ,  H01L27/10891

摘要： The present invention provides a semiconductor structure that includes an active wordline located above a semiconductor memory device and a passive wordline located adjacent to said active wordline and above an active area of a substrate. In accordance with the present invention, the passive wordline is separated from the active area by a pad nitride. The present invention also provides methods that are capable of forming the inventive semiconductor structure.

摘要翻译： 本发明提供一种半导体结构，其包括位于半导体存储器件上方的有源字线和位于所述有源字线附近并位于衬底的有效区域之上的被动字线。 根据本发明，被动字线通过衬垫氮化物与有源区分离。 本发明还提供了能够形成本发明的半导体结构的方法。

公开(公告)号：US20060019443A1

公开(公告)日：2006-01-26

申请号：US10710566

申请日：2004-07-21

申请人： Deok-kee Kim ,  Ramachandra Divakaruni ,  Hiroyuki Akatsu ,  George Worth ,  Jay Strane ,  Byeong Kim

发明人： Deok-kee Kim ,  Ramachandra Divakaruni ,  Hiroyuki Akatsu ,  George Worth ,  Jay Strane ,  Byeong Kim

IPC分类号： H01L21/467 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  H01L21/31053 ,  H01L27/10841 ,  H01L27/10897

摘要： Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.

摘要翻译： 通过减少各个差异化区域中的结构之间的高度/台阶高差，可以提高具有差异化区域（例如存储器的阵列和支撑区域）的集成电路的制造产量，并且与顶部氧化物早期（TOE）和顶部 氧化物晚期过程。 新颖的平面化技术避免了由于刮擦，碎裂或凹陷而导致的有源器件，隔离结构等的损坏，这对于使用TON工艺提高制造产量特别有效，并且当平均高度/台阶高度基本相等时也使用TOE和TOL工艺。 还可以使用诸如多晶硅的替代掩模材料来简化和/或改进工艺的控制。