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公开(公告)号：US20160275014A1
公开(公告)日：2016-09-22
申请号：US15032329
申请日：2013-10-31
摘要： According to an example, a processor generates a memory access request and sends the memory access request to a memory module. The processor receives data from the memory module in response to the memory access request when a memory device in the memory module for the memory access request is busy and unable to execute the memory access request.
摘要翻译： 根据示例，处理器生成存储器访问请求并将存储器访问请求发送到存储器模块。 当用于存储器访问请求的存储器模块中的存储器设备忙并且不能执行存储器访问请求时，处理器响应于存储器访问请求从存储器模块接收数据。
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公开(公告)号：US20180253131A1
公开(公告)日：2018-09-06
申请号：US15760617
申请日：2015-09-21
IPC分类号： G06F1/26 , G06F1/30 , G06F12/0804 , G06F11/10
摘要： Example implementations relate to a server node shutdown. For example, a system includes a control module and a secondary power supply. The control module includes a detect engine to detect an even that triggers a sequenced shutdown of a server node and prevent execution of the sequenced shutdown and execution of a data transfer. The control module also includes an initiate engine to initiate a data backup process, by a basic input/output system (BIOS) of the server node, to write data from a volatile memory location of the server node to a non-volatile memory location of the server node. The secondary power supply is to support the data backup process.
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公开(公告)号：US10684664B2
公开(公告)日：2020-06-16
申请号：US15314785
申请日：2014-07-31
发明人： Raghavan V. Venugopal , Patrick A. Raymond , William C. Hallowell , Han Wang , Chin-Lung Chiang , Jyun-Jie Wang
摘要： A test and diagnostics circuit, methods and systems are described. An example test and diagnostics circuit includes a controller and a power monitor coupled to the controller. A load switch on the test and diagnostics circuit selectably implements a load from among multiple load values to test a computing and/or data storage system. The test and diagnostics circuit includes circuitry connecting the controller, the power monitor and the load switch to receive a test enable signal from a non-dedicated pin in a non-volatile dual inline memory module (NV-DIMM) slot to implement a test operation on the system.
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公开(公告)号：US10788872B2
公开(公告)日：2020-09-29
申请号：US15760617
申请日：2015-09-21
IPC分类号： G06F1/30 , G06F1/26 , G06F11/14 , G06F11/10 , G06F12/0804
摘要： Example implementations relate to a server node shutdown. For example, a system includes a control module and a secondary power supply. The control module includes a detect engine to detect an even that triggers a sequenced shutdown of a server node and prevent execution of the sequenced shutdown and execution of a data transfer. The control module also includes an initiate engine to initiate a data backup process, by a basic input/output system (BIOS) of the server node, to write data from a volatile memory location of the server node to a non-volatile memory location of the server node. The secondary power supply is to support the data backup process.
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公开(公告)号：US10402324B2
公开(公告)日：2019-09-03
申请号：US15032329
申请日：2013-10-31
IPC分类号： G06F12/0802 , G06F13/38
摘要： According to an example, a processor generates a memory access request and sends the memory access request to a memory module. The processor receives data from the memory module in response to the memory access request when a memory device in the memory module for the memory access request is busy and unable to execute the memory access request.
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公开(公告)号：US09727462B2
公开(公告)日：2017-08-08
申请号：US14435167
申请日：2013-01-30
IPC分类号： G06F3/06 , G06F12/0804 , G11C14/00
CPC分类号： G06F12/0804 , G06F3/0619 , G06F3/0656 , G06F3/0685 , G06F2003/0691 , G06F2212/1032 , G06F2212/202 , G11C14/0018
摘要： During runtime of a system, a memory controller is caused to relinquish control of a memory module that includes a volatile memory and a non-volatile memory. After the triggering, an indication is activated to the memory module, the indication causing a backup operation in the memory module, the backup operation being controlled by an internal controller in the memory module, and the backup operation involving a transfer of data from the volatile memory to the non-volatile memory in the memory module.
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