公开(公告)号：US20090003104A1

公开(公告)日：2009-01-01

申请号：US12155512

申请日：2008-06-05

申请人： Hi-Choon LEE

发明人： Hi-Choon LEE

IPC分类号： G11C29/00

CPC分类号： G11C29/26 ,  G11C2029/1202

摘要： A test circuit and method for use in a semiconductor memory device is provided. The test method for use in a semiconductor memory device including a plurality of memory blocks may include sequentially enabling a plurality of word lines by applying a stress to the wordlines and performing a test operation, in response to sequentially applied test addresses, each of the word lines being sequentially selected from the plurality of memory blocks and enabled.

摘要翻译： 提供了一种用于半导体存储器件的测试电路和方法。 在包括多个存储块的半导体存储器件中使用的测试方法可以包括通过对字线施加应力并且响应于顺序施加的测试地址来执行测试操作来顺序启用多个字线，每个字 从多个存储器块顺序选择并使能。

公开(公告)号：US20070070749A1

公开(公告)日：2007-03-29

申请号：US11558398

申请日：2006-11-09

申请人： Hi-Choon LEE ,  Wol-Jin LEE

发明人： Hi-Choon LEE ,  Wol-Jin LEE

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/229

摘要： A semiconductor memory device includes first and second global data line pairs connected to a local data line pair, allowing a reduced pre-charge voltage that lowers current consumption and increases operating speed. Also included are a sense amplifier for amplifying data of the second global data line pair and outputting the amplified data to a data line, and a write driver for outputting data of the data line to the first global data line pair during a write operation. Switching circuits are connected between the first and second global data line pairs, and the local data line and the first global data line pairs. The memory device further includes a first global data line pre-charge circuit for pre-charging the first global data line pair to a first voltage level, and a second global data line pre-charge circuit for pre-charging the second global data line pair to a second voltage level.

摘要翻译： 半导体存储器件包括连接到本地数据线对的第一和第二全局数据线对，允许减少的预充电电压降低电流消耗并增加操作速度。 还包括用于放大第二全局数据线对的数据并将放大的数据输出到数据线的读出放大器，以及用于在写入操作期间将数据线的数据输出到第一全局数据线对的写入驱动器。 开关电路连接在第一和第二全局数据线对之间，以及本地数据线和第一全局数据线对之间。 存储器件还包括用于将第一全局数据线对预充电到第一电压电平的第一全局数据线预充电电路和用于对第二全局数据线对进行预充电的第二全局数据线预充电电路 达到第二电压电平。

公开(公告)号：US20090116305A1

公开(公告)日：2009-05-07

申请号：US12260206

申请日：2008-10-29

申请人： Chris Ji-Yoon SON ,  Hi-Choon LEE

发明人： Chris Ji-Yoon SON ,  Hi-Choon LEE

IPC分类号： G11C7/00 ,  G11C8/08 ,  G11C5/14

CPC分类号： G11C8/08 ,  G11C11/406 ,  G11C11/4087 ,  G11C2211/4065 ,  G11C2211/4067

摘要： A word line driver for use in a semiconductor memory device includes a boosted voltage generator, a sub word line driver and a main word line driver. The boosted voltage generator generates a boosted voltage by receiving an internal power supply voltage and pumping electric charge. The sub word line driver receives the internal power supply voltage and activates a boosted voltage control signal after supplying the internal power supply voltage to a boost node in a command operating mode. The main word line driver enables a word line by supplying the boosted voltage to the boost node in response to the boosted voltage control signal in a normal operating mode, and enables the word line with the boosted voltage after boosting the word line to the internal power supply voltage by changing the boost node from the internal power supply voltage to the boosted voltage in the command operating mode.

摘要翻译： 用于半导体存储器件的字线驱动器包括升压电压发生器，子字线驱动器和主字线驱动器。 升压电压发生器通过接收内部电源电压和泵送电荷而产生升压电压。 子字线驱动器接收内部电源电压，并且在命令操作模式下将内部电源电压提供给升压节点之后激活升压电压控制信号。 主字符驱动器通过在正常工作模式下响应于升压电压控制信号而将升压电压提供给升压节点来实现字线，并且在将字线升压到内部电源之后使得具有升压电压的字线 在指令运行模式下，通过将升压节点从内部电源电压改变为升压电压来提供电压。

公开(公告)号：US20080052482A1

公开(公告)日：2008-02-28

申请号：US11775780

申请日：2007-07-10

申请人： Joo-Sun CHOI ,  Won-Chang JUNG ,  Hi-Choon LEE ,  Sung-Min YIM ,  Chul-Woo PARK ,  Won-Il BAE

发明人： Joo-Sun CHOI ,  Won-Chang JUNG ,  Hi-Choon LEE ,  Sung-Min YIM ,  Chul-Woo PARK ,  Won-Il BAE

IPC分类号： G06F12/00

CPC分类号： G11C7/1045 ,  G11C7/1072

摘要： In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control signal having a logic level that varies depending on whether or not an output order of burst data is reordered. The latency control unit may control a latency value in response to the latency control signal. The semiconductor memory device and the method of controlling the latency value responsive to a reordering of the burst data allow for an optimally fast memory access time.

摘要翻译： 在一个实施例中，半导体存储器件包括响应于突发数据的输出顺序是否被重新排序而被控制的时钟等待时间。 半导体存储器件可以包括控制单元和等待时间控制单元。 控制单元可以生成具有根据突发数据的输出顺序是否被重新排列而变化的逻辑电平的等待时间控制信号。 延迟控制单元可以响应于等待时间控制信号来控制等待时间值。 半导体存储器件和响应于突发数据的重排序来控制延迟值的方法允许最佳的快速存储器存取时间。