公开(公告)号：US5060034A

公开(公告)日：1991-10-22

申请号：US427252

申请日：1989-10-25

申请人： Hideaki Shimizu ,  Nobuyuki Yamamura ,  Hiroyasu Yamada ,  Haruo Wakai ,  Hiroshi Matsumoto

发明人： Hideaki Shimizu ,  Nobuyuki Yamamura ,  Hiroyasu Yamada ,  Haruo Wakai ,  Hiroshi Matsumoto

IPC分类号： H01L27/115

CPC分类号： H01L27/115

摘要： A memory device includes a memory element composed of a first thin film transistor having a memory function, and a select element composed of a second thin film transistor for selecting the memory element. A gate insulation film of the first thin film transistor has a charge storage function. A gate insulation film of the second thin film transistor does not have any charge storage function. If a plurality of the memory devices are arranged in matrix form, this configuration can be used as E.sup.2 PROM. By forming the first and second thin film transistors simultaneously, it is possible to form the first and second thin film transistors easily in the simple manufacturing steps.

公开(公告)号：US5327001A

公开(公告)日：1994-07-05

申请号：US41537

申请日：1993-04-01

申请人： Haruo Wakai ,  Nobuyuki Yamamura ,  Syunichi Sato ,  Minoru Kanbara

发明人： Haruo Wakai ,  Nobuyuki Yamamura ,  Syunichi Sato ,  Minoru Kanbara

IPC分类号： G02F1/1362 ,  H01L27/01 ,  H01L27/13 ,  H01L29/78

CPC分类号： G02F1/136209 ,  G02F1/136227

摘要： A TFT array has a plurality of gate lines and a plurality of drain lines formed on a transparent insulating substrate. The gate lines intersect with the drain lines. TFTs are formed at the intersections of the gate lines and the drain lines. An opaque film is formed above the gate lines, the drain lines, and the TFTs, allowing no passage of light passing through the gaps between the transparent electrode, on the one hand, and the gate and drain lines, on the other hand. Therefore, when the TFT array is incorporated into a liquid-crystal display, the display will display high-contrast images.

摘要翻译： TFT阵列具有形成在透明绝缘基板上的多条栅极线和多条漏极线。 栅极线与漏极线相交。 TFT形成在栅极线和漏极线的交点处。 另一方面，在栅极线，漏极线和TFT的上方形成不透明的膜，从而允许一方面透过透明电极与栅极和漏极线之间的间隙的光通过。 因此，当TFT阵列结合到液晶显示器中时，显示器将显示高对比度图像。

公开(公告)号：US5032883A

公开(公告)日：1991-07-16

申请号：US241304

申请日：1988-09-07

申请人： Haruo Wakai ,  Nobuyuki Yamamura ,  Syunichi Sato ,  Minoru Kanbara

发明人： Haruo Wakai ,  Nobuyuki Yamamura ,  Syunichi Sato ,  Minoru Kanbara

IPC分类号： G02F1/1333 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/41733 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/133357 ,  G02F2001/13606

摘要： A TFT of the present invention includes a transparent insulative substrate, a gate electrode formed on the substrate, a gate insulating film formed on at least the gate electrode, a semiconductor film formed at a position on the gate insulating film corresponding to the gate electrode, source and drain electrodes arranged on the semiconductor film so as to form a channel portion, a transparent insulating film covering the source and drain electrodes and the semiconductor film, and a transparent electrode connected to the source electrode. A through hole is formed in the transparent insulating film above the source electrode. The transparent electrode is formed on a portion of the transparent insulating film except for a portion above the channel portion on the semiconductor film.

摘要翻译： 本发明的TFT包括透明绝缘基板，形成在基板上的栅电极，至少形成在栅电极上的栅极绝缘膜，形成在对应于栅电极的栅极绝缘膜上的位置处的半导体膜， 排列在半导体膜上的源极和漏极，以形成沟道部分，覆盖源电极和漏极以及半导体膜的透明绝缘膜，以及连接到源电极的透明电极。 在源极上方的透明绝缘膜上形成有通孔。 透明电极形成在透明绝缘膜的除了半导体膜上的沟道部分之上的部分之外。

公开(公告)号：US5166085A

公开(公告)日：1992-11-24

申请号：US503269

申请日：1990-04-02

申请人： Haruo Wakai ,  Nobuyuki Yamamura ,  Syunichi Sato ,  Minoru Kanbara

发明人： Haruo Wakai ,  Nobuyuki Yamamura ,  Syunichi Sato ,  Minoru Kanbara

IPC分类号： G02F1/1333 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/78696 ,  G02F1/1368 ,  H01L27/12 ,  G02F1/136227 ,  G02F2001/133357

摘要： First, a gate metal layer, a gate insulating film, a semiconductor layer, an n-type semiconductor layer, and an ohmic metal layer formed on a substrate in the order mentioned. Then, the film and the layers are patterned into those having the same shape and size. Next, a source metal layer and a drain metal layer are formed on the ohmic metal layer. Further, a portion of the ohmic metal layer, a portion of said source metal layer, and a portion of said drain metal layer are etched, thereby forming a channel portion. Finally, a transparent electrode is formed on the source metal layer, thus manufacturing a TFT. Since the film and the layer, the major components of the TFT, are sequentially formed, and are patterned simultaneously, the TFT can be manufacture with high yield. Further, since the transparent electrode is formed on the uppermost layer, i.e., the source metal layer, the pixel has a great opening ratio.

摘要翻译： 首先，按照上述顺序在基板上形成栅极金属层，栅极绝缘膜，半导体层，n型半导体层和欧姆金属层。 然后，将膜和层图案化成具有相同形状和尺寸的那些。 接着，在欧姆金属层上形成源极金属层和漏极金属层。 此外，欧姆金属层的一部分，所述源极金属层的一部分和所述漏极金属层的一部分被蚀刻，从而形成沟道部分。 最后，在源极金属层上形成透明电极，制造TFT。 由于TFT和TFT的主要部分依次形成，并且被图案化，TFT可以高产率制造。 此外，由于透明电极形成在最上层即源极金属层上，所以像素具有大的开口率。

公开(公告)号：US5229644A

公开(公告)日：1993-07-20

申请号：US831002

申请日：1992-02-05

申请人： Haruo Wakai ,  Nobuyuki Yamamura ,  Syunichi Sato ,  Minoru Kanbara

发明人： Haruo Wakai ,  Nobuyuki Yamamura ,  Syunichi Sato ,  Minoru Kanbara

IPC分类号： G02F1/1333 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/78696 ,  G02F1/1368 ,  H01L27/12 ,  G02F1/136227 ,  G02F2001/133357

摘要： A TFT is formed on a transparent insulative substrate, and includes a gate electrode, a gate insulating film, a semiconductor film which has a channel portion, source and drain electrodes. An insulating film is formed on the TFT so as to cover at least the drain electrode and the gate insulating film. A transparent electrode is formed on at least part of insulating film except for a portion above the channel portion on the semiconductor film. The transparent electrode is electrically connected to the source electrode via a through hole which is formed on the insulating film at a position of the source electrode.

摘要翻译： 在透明绝缘基板上形成TFT，具有栅电极，栅极绝缘膜，具有沟道部的半导体膜，源电极和漏电极。 在TFT上形成绝缘膜，至少覆盖漏电极和栅极绝缘膜。 绝缘膜的至少一部分上形成透明电极，除了半导体膜上的沟道部分上方的部分。 透明电极通过在源电极的位置处形成在绝缘膜上的通孔与源电极电连接。

公开(公告)号：US5055899A

公开(公告)日：1991-10-08

申请号：US503270

申请日：1990-04-02

申请人： Haruo Wakai ,  Nobuyuki Yamamura ,  Syunichi Sato ,  Minoru Kanbara

发明人： Haruo Wakai ,  Nobuyuki Yamamura ,  Syunichi Sato ,  Minoru Kanbara

IPC分类号： G02F1/1333 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/41733 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/133357 ,  G02F2001/13606

摘要： A thin film transistor comprising a gate electrode, a gate insulating film, and a semiconductor layer, which have the same shape and the same size and stacked one upon another. The transistor further comprises an n-type semiconductor layer formed on the semiconductor layer, an ohmic electrode formed on the n-type semiconductor layer, and a source electrode and a drain electrode both formed on the ohmic electrode. Further, a transparent electrode is electrically connected to the source electrode. The thin film transistor has no step portions. Therefore, the transistor can be manufactured with high yield, and forms a pixel having a high opening ratio.

摘要翻译： 一种薄膜晶体管，包括具有相同形状和相同尺寸并且彼此堆叠的栅电极，栅极绝缘膜和半导体层。 晶体管还包括形成在半导体层上的n型半导体层，形成在n型半导体层上的欧姆电极，以及均匀地形成在欧姆电极上的源电极和漏电极。 此外，透明电极电连接到源电极。 薄膜晶体管没有台阶部分。 因此，可以以高产率制造晶体管，并形成具有高开口率的像素。

公开(公告)号：US5003356A

公开(公告)日：1991-03-26

申请号：US503268

申请日：1990-04-02

申请人： Haruo Wakai ,  Nobuyuki Yamamura ,  Syunichi Sato ,  Minoru Kanbara

发明人： Haruo Wakai ,  Nobuyuki Yamamura ,  Syunichi Sato ,  Minoru Kanbara

IPC分类号： G02F1/1333 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/41733 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/133357 ,  G02F2001/13606

摘要： A TFT array having a plurality of gate lines and a plurality of drain lines formed on a transparent substrate. The gate lines intersect with the drain lines. TFT are formed at the intersections of the gate lines and the drain lines. An insulating film is formed on the drain lines and the drain electrodes of the TFTs. Pixel electrodes are formed, each overlapping the corresponding gate line and the corresponding drain line. The pixel electrode has a large area and thus, have a high opening ratio. The TFT array can, therefore, help to provide a liquid crystal display having high contrast.

摘要翻译： 一种具有形成在透明基板上的多条栅极线和多条漏极线的TFT阵列。 栅极线与漏极线相交。 TFT形成在栅极线和漏极线的交点处。 在TFT的漏极线路和漏极电极上形成绝缘膜。 形成像素电极，每个重叠相应的栅极线和相应的漏极线。 像素电极的面积大，因此具有高的开口率。 因此，TFT阵列有助于提供具有高对比度的液晶显示器。

公开(公告)号：US5545576A

公开(公告)日：1996-08-13

申请号：US425894

申请日：1995-04-21

申请人： Hiroshi Matsumoto ,  Haruo Wakai ,  Hiroyasu Joubettou

发明人： Hiroshi Matsumoto ,  Haruo Wakai ,  Hiroyasu Joubettou

IPC分类号： G02F1/1368 ,  H01L21/77 ,  H01L21/84 ,  H01L29/45 ,  H01L29/786 ,  H01L21/786

CPC分类号： H01L29/78696 ,  H01L27/1214 ,  H01L29/458 ,  H01L29/78618 ,  G02F1/1368 ,  Y10S148/102

摘要： A gate electrode, a semiconductor thin film, a channel protecting film and a photoresist are accumulated on the overall surface of a transparent substrate on which a gate electrode and a gate line are formed. Ultraviolet rays are irradiated through the substrate so that the photoresist and the channel protecting film are self-aligned with respect to the gate electrode and the gate line. A mask is formed on the channel protecting film so as to extend in a direction perpendicular to the channel protecting film. The channel protecting film and the semiconductor thin film are etched using the mask. As a result, the semiconductor thin film and the channel protecting film are patterned without positional deviation so as to have the same width W. Therefore, it is possible to reduce the thin film transistor forming region and the number of steps of the manufacturing process.

摘要翻译： 栅电极，半导体薄膜，沟道保护膜和光致抗蚀剂积聚在形成有栅电极和栅极线的透明基板的整个表面上。 通过基板照射紫外线，使得光致抗蚀剂和沟道保护膜相对于栅电极和栅极线自对准。 在沟道保护膜上形成掩模，以便在与沟道保护膜垂直的方向上延伸。 使用掩模蚀刻沟道保护膜和半导体薄膜。 结果，半导体薄膜和沟道保护膜被图案化而没有位置偏移，从而具有相同的宽度W.因此，可以减小薄膜晶体管形成区域和制造工艺的步骤数量。

公开(公告)号：US5736436A

公开(公告)日：1998-04-07

申请号：US561045

申请日：1995-11-20

申请人： Hiroshi Matsumoto ,  Haruo Wakai ,  Hiroyasu Joubettou

发明人： Hiroshi Matsumoto ,  Haruo Wakai ,  Hiroyasu Joubettou

IPC分类号： G02F1/1368 ,  H01L21/77 ,  H01L21/84 ,  H01L29/45 ,  H01L29/786 ,  H01L21/00 ,  H01L21/44

CPC分类号： H01L29/78696 ,  H01L27/1214 ,  H01L29/458 ,  H01L29/78618 ,  G02F1/1368 ,  Y10S148/102

摘要： A gate electrode, a semiconductor thin film, a channel protecting film and a photoresist are accumulated on the overall surface of a transparent substrate on which a gate electrode and a gate line are formed. Ultraviolet rays are irradiated through the substrate so that the photoresist and the channel protecting film are self-aligned with respect to the gate electrode and the gate line. A mask is formed on the channel protecting film so as to extend in a direction perpendicular to the channel protecting film. The channel protecting film and the semiconductor thin film are etched using the mask. As a result, the semiconductor thin film and the channel protecting film are patterned without positional deviation so as to have the same width W. Therefore, it is possible to reduce the thin film transistor forming region and the number of steps of the manufacturing process.

摘要翻译： 栅电极，半导体薄膜，沟道保护膜和光致抗蚀剂积聚在形成有栅电极和栅极线的透明基板的整个表面上。 通过基板照射紫外线，使得光致抗蚀剂和沟道保护膜相对于栅电极和栅极线自对准。 在沟道保护膜上形成掩模，以便在与沟道保护膜垂直的方向上延伸。 使用掩模蚀刻沟道保护膜和半导体薄膜。 结果，半导体薄膜和沟道保护膜被图案化而没有位置偏移，从而具有相同的宽度W.因此，可以减小薄膜晶体管形成区域和制造工艺的步骤数量。

公开(公告)号：US5694061A

公开(公告)日：1997-12-02

申请号：US621112

申请日：1996-03-22

申请人： Katsuhiko Morosawa ,  Haruo Wakai

发明人： Katsuhiko Morosawa ,  Haruo Wakai

IPC分类号： G09G3/36 ,  H03K19/0944 ,  H03K4/58

CPC分类号： G09G3/3688 ,  G09G3/3648 ,  G09G3/3677 ,  H03K19/09441

摘要： A semiconductor device having at least first and second MIS transistors of a same P or N conductive type. The first MIS transistor has a first data terminal which receives a high potential Vdd, and the second MIS transistor has a first data terminal which receives a low potential GND lower than the high potential Vdd. An output terminal is coupled to second data terminals of the first and second MIS transistors. A first input terminal is connected to a gate of the first MIS transistor for supplying a non-inverted signal. A second input terminal is directly connected to a gate of one of the first and second MIS transistors for supplying an inverted signal having a reverse polarity to the non-inverted signal and which is synchronized with the non-inverted signal. An output voltage compensating circuit is connected between one of (i) the output terminal and the first input terminal and (ii) the output terminal and the second input terminal. The output voltage compensating circuit prevents the lower potential of an output signal from rising if the semiconductor device includes PMIS transistors, and prevents the higher potential of the output signal from falling if the semiconductor device includes NMIS transistors.

摘要翻译： 具有至少具有相同P或N导电类型的第一和第二MIS晶体管的半导体器件。 第一MIS晶体管具有接收高电位Vdd的第一数据端子，第二MIS晶体管具有接收低于高电位Vdd的低电位GND的第一数据端子。 输出端耦合到第一和第二MIS晶体管的第二数据端。 第一输入端子连接到第一MIS晶体管的栅极，用于提供非反相信号。 第二输入端子直接连接到第一和第二MIS晶体管之一的栅极，用于向非反相信号提供具有相反极性的反相信号，并且与非反相信号同步。 输出电压补偿电路连接在（i）输出端子和第一输入端子之间，以及（ii）输出端子和第二输入端子之一。 如果半导体器件包括PMIS晶体管，则输出电压补偿电路防止输出信号的较低电位上升，并且如果半导体器件包括NMIS晶体管，则防止输出信号的较高电位下降。