公开(公告)号：US08809986B2

公开(公告)日：2014-08-19

申请号：US13321714

申请日：2009-05-29

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Yuji Nishibe

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Yuji Nishibe

IPC分类号： H01L29/66

CPC分类号： H01L29/7815 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095

摘要： Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current. In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ∑ i = 1 n ⁢ ( R Mi × k Mi ) - ∑ i = 1 n ⁢ ( R Si × k Si ) ] / ∑ i = 1 n ⁢ ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.

摘要翻译： 提供了能够降低电流感测比的温度变化并准确地检测电流的半导体器件。 在半导体器件中，调整每个半导体层的杂质浓度和厚度中的至少一个，使得由以下等式计算的值小于预定值：[Σi = 1 n（R Mi×k Mi ） - Σi = 1 n（R Si×k Si）] /Σi = 1 n（R Mi×k Mi）其中，第i个半导体层的温度依赖电阻变化率（i = 1〜 n）的主要元素域是RMi; 主元件区域的第i个半导体层相对于整个主要元件区域的电阻比为kMi; 感测元件畴的第i个半导体层的温度依赖性电阻变化率为RSi; 并且感测元件畴的第i个半导体层与整个感测元件畴的电阻比为kSi。

公开(公告)号：US08933483B2

公开(公告)日：2015-01-13

申请号：US14074212

申请日：2013-11-07

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Yuji Nishibe

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Yuji Nishibe

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L29/7815 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095

摘要： Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ∑ i = 1 n ⁢ ( R Mi × k Mi ) - ∑ i = 1 n ⁢ ( R Si × k Si ) ] / ∑ i = 1 n ⁢ ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.

摘要翻译： 提供了能够降低电流感测比的温度变化并精确检测电流的半导体器件。在半导体器件中，调整每个半导体层的杂质浓度和厚度中的至少一个，使得通过a 以下等式小于预定值：[Σi = 1 n（R Mi×k Mi） - Σi = 1 n（R Si×k Si）] /Σi = 1 n（R Mi×k Mi）其中主要元素域的第i个半导体层（i = 1至n）的温度依赖性电阻变化率为RMi; 主元件区域的第i个半导体层相对于整个主要元件区域的电阻比为kMi; 感测元件畴的第i个半导体层的温度依赖性电阻变化率为RSi; 并且感测元件畴的第i个半导体层与整个感测元件畴的电阻比为kSi。

公开(公告)号：US20120068296A1

公开(公告)日：2012-03-22

申请号：US13321714

申请日：2009-05-29

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Yuji Nishibe

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Yuji Nishibe

IPC分类号： H01L29/66

CPC分类号： H01L29/7815 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095

摘要： Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ∑ i = 1 n  ( R Mi × k Mi ) - ∑ i = 1 n  ( R Si × k Si ) ] / ∑ i = 1 n  ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.

摘要翻译： 提供了能够降低电流感测比的温度变化并精确检测电流的半导体器件。在半导体器件中，调整每个半导体层的杂质浓度和厚度中的至少一个，使得通过a 以下等式小于预定值：[Σi = 1 n（R Mi×k Mi） - Σi = 1 n（R Si×k Si）] /Σi = 1 n（R Mi×k Mi）其中主要元素域的第i个半导体层（i = 1至n）的温度依赖性电阻变化率为RMi; 主元件区域的第i个半导体层相对于整个主要元件区域的电阻比为kMi; 感测元件畴的第i个半导体层的温度依赖性电阻变化率为RSi; 并且感测元件畴的第i个半导体层与整个感测元件畴的电阻比为kSi。

公开(公告)号：US08076718B2

公开(公告)日：2011-12-13

申请号：US11666461

申请日：2005-09-28

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

摘要： The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.

摘要翻译： 本发明的目的是提供一种绝缘栅型半导体器件及其制造方法，其中实现了高的击穿电压和紧凑性。 半导体器件具有形成在单元区域中的栅极沟槽和P浮动区域，并且具有形成在端子区域中的端子沟槽和P浮动区域。 此外，三个端子沟槽的端子沟槽具有与栅极沟槽类似的结构，而另一个端子沟槽具有填充绝缘物质如氧化硅的结构。 此外，P浮动区域51是通过从栅极沟槽的底表面注入杂质形成的区域，并且P浮动区域是通过从端子沟槽的底表面注入杂质而形成的区域。

公开(公告)号：US07999312B2

公开(公告)日：2011-08-16

申请号：US12223871

申请日：2007-01-26

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi

IPC分类号： H01L29/66 ,  H01L29/732 ,  H01L29/78 ,  H01L21/426

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor 100 has a P− body region and an N− drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P− body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P−− diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P− body region and the P diffusion region, is formed. The P−− diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P−− diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.

摘要翻译： 半导体100具有从其上表面侧开始的顺序的P-体区域和N-漂移区域。 形成通过P-体区域的栅极沟槽和端子沟槽。 各个沟槽在其底部被P扩散区包围。 栅极沟槽在其中形成栅电极。 形成了与栅极沟槽的长度方向上的端部接触并且浓度低于P体区域和P扩散区域的P扩散区域。 当栅极电压关闭时，P扩散区在P扩散区之前耗尽。 当栅极电压接通时，P扩散区域用作到P扩散区域的空穴供应路径。

公开(公告)号：US20100224932A1

公开(公告)日：2010-09-09

申请号：US12223871

申请日：2007-01-26

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi

IPC分类号： H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor 100 has a P− body region and an N− drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P− body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P−− diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P− body region and the P diffusion region, is formed. The P−− diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P−− diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.

摘要翻译： 半导体100具有从其上表面侧开始的顺序的P-体区域和N-漂移区域。 形成通过P-体区域的栅极沟槽和端子沟槽。 各个沟槽在其底部被P扩散区包围。 栅极沟槽在其中形成栅电极。 形成了与栅极沟槽的长度方向上的端部接触并且浓度低于P体区域和P扩散区域的P扩散区域。 当栅极电压关闭时，P扩散区在P扩散区之前耗尽。 当栅极电压接通时，P扩散区域用作到P扩散区域的空穴供应路径。

公开(公告)号：US07470953B2

公开(公告)日：2008-12-30

申请号：US10573793

申请日：2004-10-06

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Akira Kuroyanagi ,  Yasushi Okura ,  Norihito Tokura

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Akira Kuroyanagi ,  Yasushi Okura ,  Norihito Tokura

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7811

摘要： The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P− body region 41, and N− drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 incorporates the gate electrode 22. A P floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.

摘要翻译： 本发明旨在提供可以容易地制造的绝缘栅型半导体器件及其制造方法，同时实现更高的耐压设计和较低的导通电阻设计。 半导体器件包括N +源极区31，N +漏极区11，P-体区41和N漂移区12.通过挖掘半导体器件的上侧的一部分，形成栅沟槽21。 栅极沟槽21包含栅电极22.P浮动区51设置在栅极沟槽21的下方。可以形成与栅极沟槽21的深度不同的另外的沟槽35，设置在沟槽25下方的P浮动区域54。

公开(公告)号：US09640651B2

公开(公告)日：2017-05-02

申请号：US15116288

申请日：2014-10-06

申请人： Hidefumi Takaya ,  Jun Saito ,  Akitaka Soeno ,  Kimimori Hamada ,  Shoji Mizuno ,  Sachiko Aoi ,  Yukihiko Watanabe

发明人： Hidefumi Takaya ,  Jun Saito ,  Akitaka Soeno ,  Kimimori Hamada ,  Shoji Mizuno ,  Sachiko Aoi ,  Yukihiko Watanabe

IPC分类号： H01L29/94 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/761 ,  H01L29/16

CPC分类号： H01L29/7811 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.

公开(公告)号：US20080087951A1

公开(公告)日：2008-04-17

申请号：US11666461

申请日：2005-09-28

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihiko Tokura

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihiko Tokura

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

摘要： The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.

摘要翻译： 本发明的目的是提供一种绝缘栅型半导体器件及其制造方法，其中实现了高的击穿电压和紧凑性。 半导体器件具有形成在单元区域中的栅极沟槽和P浮动区域，并且具有形成在端子区域中的端子沟槽和P浮动区域。 此外，三个端子沟槽的端子沟槽具有与栅极沟槽类似的结构，而另一个端子沟槽具有填充绝缘物质如氧化硅的结构。 此外，P浮动区域51是通过从栅极沟槽的底表面注入杂质形成的区域，并且P浮动区域是通过从端子沟槽的底表面注入杂质而形成的区域。

公开(公告)号：US20060289928A1

公开(公告)日：2006-12-28

申请号：US10573793

申请日：2004-10-06

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Akira Kuroyanagi ,  Yasushi Okura ,  Norihito Tokura

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Akira Kuroyanagi ,  Yasushi Okura ,  Norihito Tokura

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7811

摘要： The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P− body region 41, and N− drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.

摘要翻译： 本发明旨在提供可以容易地制造的绝缘栅型半导体器件及其制造方法，同时实现更高的耐压设计和较低的导通电阻设计。 半导体器件包括N +源极区31，N +漏极区11，P-体区41和N漂移区12.通过挖掘半导体器件的上侧的一部分，形成栅沟槽21。 栅极沟槽21浮置区域51设置在栅极沟槽21的下方。可以形成与栅极沟槽21的深度不同的另外的沟槽35，P浮动区域54设置在沟槽25的下方。