公开(公告)号：US07768066B2

公开(公告)日：2010-08-03

申请号：US12179549

申请日：2008-07-24

申请人： Hidekatsu Onose ,  Hiroyuki Takazawa

发明人： Hidekatsu Onose ,  Hiroyuki Takazawa

IPC分类号： H01L29/94

CPC分类号： H01L29/7828 ,  H01L25/18 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7391 ,  H01L2924/0002 ,  H01L2924/00

摘要： A UMOSFET is capable of reducing a threshold voltage and producing a large saturation current. A typical UMOSFET according to the present invention includes: an N+ type SiC substrate constituting a drain layer; an N− type SiC layer that is in contact with the drain layer and constitutes a drift layer; a P type body layer formed on the drift layer and being a semiconductor layer; an N+ type SiC layer constituting a source layer; a trench extending from the source layer to a predetermined location placed in the drift layer; a P type electric field relaxation region provided around and outside a bottom portion of the trench; and a channel region extending from the N+ type source layer to the P type electric field relaxation region and having an impurity concentration higher than that of the N− type drift layer and lower than that of the P type body layer.

摘要翻译： UMOSFET能够降低阈值电压并产生大的饱和电流。 根据本发明的典型的UMOSFET包括：构成漏极层的N +型SiC衬底; 与漏极层接触并构成漂移层的N型SiC层; 形成在所述漂移层上并且是半导体层的P型体层; 构成源极层的N +型SiC层; 从源极层延伸到放置在漂移层中的预定位置的沟槽; 设置在沟槽的底部周围和外侧的P型电场弛豫区域; 以及从N +型源极层向P型电场弛豫区域延伸并且杂质浓度高于N型漂移层的杂质浓度并低于P型体层的沟道区域。

公开(公告)号：US20090032821A1

公开(公告)日：2009-02-05

申请号：US12179549

申请日：2008-07-24

申请人： Hidekatsu Onose ,  Hiroyuki Takazawa

发明人： Hidekatsu Onose ,  Hiroyuki Takazawa

IPC分类号： H01L29/78

CPC分类号： H01L29/7828 ,  H01L25/18 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7391 ,  H01L2924/0002 ,  H01L2924/00

摘要： A UMOSFET is capable of reducing a threshold voltage and producing a large saturation current. A typical UMOSFET according to the present invention includes: an N+ type SiC substrate constituting a drain layer; an N− type SiC layer that is in contact with the drain layer and constitutes a drift layer; a P type body layer formed on the drift layer and being a semiconductor layer; an N+ type SiC layer constituting a source layer; a trench extending from the source layer to a predetermined location placed in the drift layer; a P type electric field relaxation region provided around and outside a bottom portion of the trench; and a channel region extending from the N+ type source layer to the P type electric field relaxation region and having an impurity concentration higher than that of the N− type drift layer and lower than that of the P type body layer.

摘要翻译： UMOSFET能够降低阈值电压并产生大的饱和电流。 根据本发明的典型的UMOSFET包括：构成漏极层的N +型SiC衬底; 与漏极层接触并构成漂移层的N型SiC层; 形成在所述漂移层上并且是半导体层的P型体层; 构成源极层的N +型SiC层; 从源极层延伸到放置在漂移层中的预定位置的沟槽; 设置在沟槽的底部周围和外侧的P型电场弛豫区域; 以及从N +型源极层向P型电场弛豫区域延伸并且杂质浓度高于N型漂移层的杂质浓度并低于P型体层的沟道区域。

公开(公告)号：US08227831B2

公开(公告)日：2012-07-24

申请号：US12715466

申请日：2010-03-02

申请人： Hidekatsu Onose

发明人： Hidekatsu Onose

IPC分类号： H01L29/66

CPC分类号： H01L29/8083 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/18 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66909 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor device having a junction FET having improved characteristics is provided. The semiconductor device has a junction FET as a main transistor and has a MISFET as a transistor for control. The junction FET has a first gate electrode, a first source electrode, and a first drain electrode. The MISFET has a second gate electrode, a second source electrode, and a second drain electrode. The MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET. The second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting. The first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.

摘要翻译： 提供具有改善特性的结型FET的半导体器件。 半导体器件具有作为主晶体管的结FET，并且具有MISFET作为用于控制的晶体管。 结型FET具有第一栅电极，第一源电极和第一漏电极。 MISFET具有第二栅极电极，第二源极电极和第二漏极电极。 MISFET是n沟道型MISFET，具有增强型MISFET的电特性。 MISFET的第二栅电极和第二漏电极通过短路相互连接。 结FET的第一栅电极和MISFET的第二源电极通过短路相互连接。

公开(公告)号：US20090057685A1

公开(公告)日：2009-03-05

申请号：US12176635

申请日：2008-07-21

申请人： Kazuhiro MOCHIZUKI ,  Hidekatsu Onose ,  Natsuki Yokoyama

发明人： Kazuhiro MOCHIZUKI ,  Hidekatsu Onose ,  Natsuki Yokoyama

IPC分类号： H01L29/24

CPC分类号： H01L29/1608 ,  H01L29/0804 ,  H01L29/66068 ,  H01L29/7322

摘要： In a mesa type bipolar transistor or a thyristor, since carriers injected from an emitter layer or an anode layer to a base layer or a gate layer diffuse laterally and are recombined, reduction in the size and improvement for the switching frequency is difficult.In the invention, the emitter layer or the anode layer is formed of two high-doped and low-doped layers, a semiconductor region for suppressing recombination comprising an identical semiconductor having an impurity density identical with that of the low-doped layer is present being in contact with a base layer or a gate layer and a surface passivation layer, and the width of the semiconductor region for suppressing recombination is defined equal with or longer than the diffusion length of the carrier. This provides an effect of attaining reduction in the size of the bipolar transistor or improvement of the switching frequency of the thyristor without deteriorating the performance. Further, this has an effect of greatly improving the current gain by successively stacking above the high-doped emitter layer of the bipolar transistor, a hole barrier layer, a conduction band discontinuity relaxed layer and an emitter contact layer.

摘要翻译： 在台式双极晶体管或晶闸管中，由于从发射极层或阳极层向基极层或栅极层注入的载流子横向漫射并重新组合，因此难以减小开关频率的尺寸和改善。 在本发明中，发射极层或阳极层由两个高掺杂和低掺杂层形成，用于抑制复合的半导体区域包括具有与低掺杂层的杂质密度相同的杂质密度的相同半导体， 与基底层或栅极层和表面钝化层接触，并且用于抑制复合的半导体区域的宽度被限定为等于或长于载体的扩散长度。 这提供了在不降低性能的情况下实现双极晶体管的尺寸的减小或晶闸管的开关频率的提高的效果。 此外，这具有通过连续堆叠在双极晶体管，空穴阻挡层，导带不连续松弛层和发射极接触层的高掺杂发射极层上方大大改善电流增益的效果。

公开(公告)号：US06750477B2

公开(公告)日：2004-06-15

申请号：US10121623

申请日：2002-04-15

申请人： Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Hidekatsu Onose ,  Saburo Oikawa

发明人： Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Hidekatsu Onose ,  Saburo Oikawa

IPC分类号： H01L310312

CPC分类号： H01L29/7722 ,  H01L29/1608

摘要： In a static induction transistor, in addition to a first gate layer (4), a plurality of second gate layers (41) having a shallower depth and a narrower gap therebetween than those of the first gate layer (4) are provided in an area surrounded by the first gate layer (4), thereby an SiC static induction transistor with an excellent off characteristic is realized, while ensuring a required processing accuracy during production thereof.

摘要翻译： 在静电感应晶体管中，除了第一栅极层（4）之外，还具有与第一栅极层（4）相比具有较浅深度和间隔更窄的多个第二栅极层（41） 由第一栅极层（4）包围，从而实现具有优异的截止特性的SiC静态感应晶体管，同时确保其制造期间所需的加工精度。

公开(公告)号：US06566726B1

公开(公告)日：2003-05-20

申请号：US09516501

申请日：2000-03-01

申请人： Hidekatsu Onose ,  Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Saburou Oikawa

发明人： Hidekatsu Onose ,  Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Saburou Oikawa

IPC分类号： H01L2940

CPC分类号： H01L29/0615 ,  H02M7/003

摘要： To reduce the field intensity on the termination surface, almost not affecting the on-characteristic, a drift layer is made of two layers, an n-layer and n− layer, and a termination region is formed on the surface of the above n− layer. An impurity concentration ratio between the n− layer and the n-layer is less than 1:2, and the thickness of the n− layer is less than that of a source n+ layer. Reliability can be secured even in a high temperature operation.

摘要翻译： 为了降低终端表面上的场强，几乎不影响导通特性，漂移层由n层和n层两层构成，并且在上述n-层的表面上形成端接区， 层。 n层和n层之间的杂质浓度比小于1：2，n层的厚度小于源n +层的厚度。 即使在高温操作中也可以确保可靠性。

公开(公告)号：US5652467A

公开(公告)日：1997-07-29

申请号：US507989

申请日：1995-07-27

申请人： Hidekatsu Onose ,  Shuroku Sakurada

发明人： Hidekatsu Onose ,  Shuroku Sakurada

IPC分类号： H01L23/48

CPC分类号： H01L24/72 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01082 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/30107

摘要： An auxiliary cathode lead is contacted to a cathode buffer electrode which contacts to an unit GTO arranged at the most remote region from a gate pressure contacting portion of a GTO pellet and the push-into effect of the auxiliary cathode current during the turn-off can be remarkably performed. Without inviting bad affects such as the increase in "on" voltage, it is proposed a package structure of a semiconductor which the unit GTO arranged remote from a gate is easily to perform the turn-off. The maximum turn-off current can be heightened, it can easily correspond to the increase in the diameter of the pellet according to the large current of the unit element. Further, a condenser of a snubber circuit as a protection circuit of the unit GTO in a power inverter can be small, and the snubber loss can be lessened.

摘要翻译： 辅助阴极引线与阴极缓冲电极接触，该阴极缓冲电极与GTO颗粒的栅极压力接触部分最远的区域布置的单元GTO接触，并且关断期间辅助阴极电流的推入效应 被显着地执行。 没有引起诸如“开”电压增加的不良影响，提出了一种半导体的封装结构，其中远离栅极的单元GTO易于执行关断。 可以提高最大关断电流，可以根据单元元件的大电流容易地对应于颗粒的直径的增加。 此外，作为功率逆变器中的单元GTO的保护电路的缓冲电路的电容器可以很小，并且可以减小缓冲器损耗。

公开(公告)号：US20050006649A1

公开(公告)日：2005-01-13

申请号：US10824442

申请日：2004-04-15

申请人： Takayuki Iwasaki ,  Tsutomu Yatsuo ,  Hidekatsu Onose ,  Toshiyuki Oono

发明人： Takayuki Iwasaki ,  Tsutomu Yatsuo ,  Hidekatsu Onose ,  Toshiyuki Oono

IPC分类号： H01L29/772 ,  H02M7/00 ,  H01L31/0312

CPC分类号： H02M7/003 ,  H01L29/7722

摘要： A static induction transistor includes a semiconductor substrate with an energy band gap greater than that of silicon, and the semiconductor substrate has a first gate region to which a gate electrode is connected; and a second gate region positioned within a first semiconductor region which becomes a drain region, and the first gate region is in contact with a second semiconductor region which becomes a source region. According to this construction, the OFF characteristics of the static induction transistor are improved.

摘要翻译： 静电感应晶体管包括具有比硅的能带隙大的能带隙的半导体衬底，并且半导体衬底具有连接有栅电极的第一栅极区域; 以及位于成为漏极区域的第一半导体区域内的第二栅极区域，并且第一栅极区域与成为源极区域的第二半导体区域接触。 根据该结构，能够提高静电感应晶体管的OFF特性。

公开(公告)号：US06353236B1

公开(公告)日：2002-03-05

申请号：US09396733

申请日：1999-09-15

申请人： Tsutomu Yatsuo ,  Takayuki Iwasaki ,  Hidekatsu Onose ,  Shin Kimura

发明人： Tsutomu Yatsuo ,  Takayuki Iwasaki ,  Hidekatsu Onose ,  Shin Kimura

IPC分类号： H01L310312

CPC分类号： H01C7/10 ,  H01C7/12 ,  H01L29/8605 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49431

摘要： A wide bandgap semiconductor single crystal is applied as a semiconductor substrate material of a semiconductor surge absorber, and a surge absorption operation starting voltage is set by a punchthrough of a pn junction, to obtain a semiconductor surge absorber with a repetitive operation and a high surge endurance.

摘要翻译： 应用宽带隙半导体单晶作为半导体浪涌吸收体的半导体衬底材料，通过pn结穿透来设置浪涌吸收操作启动电压，以获得具有重复操作和高浪涌的半导体浪涌吸收器 耐力。

公开(公告)号：US5629888A

公开(公告)日：1997-05-13

申请号：US182503

申请日：1994-01-18

申请人： Ryuichi Saito ,  Hidekatsu Onose ,  Yutaka Kobayashi ,  Michio Ohue

发明人： Ryuichi Saito ,  Hidekatsu Onose ,  Yutaka Kobayashi ,  Michio Ohue

IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C11/56 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L27/112 ,  H01L27/115

CPC分类号： H01L27/11502 ,  G11C11/22 ,  G11C11/5657 ,  G11C16/08 ,  G11C8/14 ,  H01L27/10805

摘要： A semiconductor memory device has a plurality of memory cells in an array, into which the memory cells data is writable, and which can subsequently be read. Each memory cell has a switching element with one terminal connected to a bit line of the array another terminal connected to at least one ferroelectric capacitor, and a control terminal connected to a word line. The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor and a capacitor other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality of ferroelectric capacitors are connected to the switching element, so that different data are writable into each.

摘要翻译： 半导体存储器件具有阵列中的多个存储器单元，存储器单元数据可写入其中，并且随后可以读取存储单元。 每个存储单元具有开关元件，一个端子连接到阵列的位线，另一个端子连接到至少一个铁电电容器，以及控制端子连接到字线。 然后可以操作电池以在施加电压时检测铁电电容器的极化变化，这不足以引起铁电电容器的状态改变。 或者，铁电电容器和除铁电电容器之外的电容器连接到开关元件。 在另一替代方案中，多个铁电电容器连接到开关元件，使得不同的数据可写入每个。