Radio receiver
    1.
    发明授权
    Radio receiver 失效
    无线电接收机

    公开(公告)号:US6122327A

    公开(公告)日:2000-09-19

    申请号:US796067

    申请日:1997-02-04

    CPC分类号: H04W56/0035 H04L27/22

    摘要: A radio receiver for a digital cellular system or the like which transmits or receives, for example, voice signals by coding them, and easily and reliably detects a synchronizing signal. A synchronizing signal FCCH is detected by converting a base band converted transmitted signal with an analog-to-digital convertor circuit 17, and then by detecting a correlation value with a predetermined reference signal.

    摘要翻译: 用于数字蜂窝系统等的无线电接收机,其通过编码它们来发送或接收例如语音信号,并且容易且可靠地检测同步信号。 通过用模数转换器电路17转换基带转换的发送信号,然后通过用预定的参考信号检测相关值来检测同步信号FCCH。

    Radio receiver
    3.
    发明授权
    Radio receiver 失效
    无线电接收机

    公开(公告)号:US5905764A

    公开(公告)日:1999-05-18

    申请号:US796068

    申请日:1997-02-04

    摘要: A radio receiver for a digital cellular system or the like corrects a doppler frequency shift with a simple arrangement. A phase difference of received data I,Q is corrected by generating an estimated signal EXn through estimation of the received data I,Q corresponding to transmitted data y estimated for the maximum likelihood by a maximum likelihood determination circuit 25, by detecting the branch metric BM, BM+, or BM- in which the estimated data is in phase with the received signal, or in the leading or trailing phase to the received signal, respectively, by detecting the phase difference of the received data I,Q from the estimated signal EXn based on the result of comparison of the branch metrics BM+, BM, and BM-, and by correcting the phase difference based on the result of detection of the phase difference.

    摘要翻译: 用于数字蜂窝系统等的无线电接收机以简单的布置校正多普勒频移。 接收数据I,Q的相位差通过对通过最大似然判定电路25对最大似然度估计的发送数据y的对应的接收数据I,Q的估计,通过检测分支量度BM ,BM +或BM-,其中估计数据与接收信号同相,或分别在接收信号的前置或后置相位,通过从估计信号EXn检测接收数据I,Q的相位差 基于分支量度BM +,BM和BM-的比较结果,并且基于相位差的检测结果校正相位差。

    Receiving system using training pattern correlation for improved signal
reception
    4.
    发明授权
    Receiving system using training pattern correlation for improved signal reception 失效
    接收系统使用训练模式相关来改善信号接收

    公开(公告)号:US5978416A

    公开(公告)日:1999-11-02

    申请号:US796069

    申请日:1997-02-04

    CPC分类号: H04L25/0236

    摘要: A transmission apparatus which can realize high demodulation efficiency even in the case where the channel characteristic is deteriorated. The same pattern data as those of the known pattern data contained in the transmitting data to be transmitted to the channel is generated on the receiving side and the correlation between said pattern data and the receiving data to be received through the channel is obtained. Then, the channel characteristic is successively estimated based on the correlation value and the receiving data will be demodulated depending upon said estimated result. Thus, since the channel characteristic can be estimated based on the receiving data, the data can be demodulated correctly even in the case where the receiving data is distorted due to the characteristic deterioration.

    摘要翻译: 即使在信道特性劣化的情况下也能够实现高解调效率的发送装置。 在接收侧生成与要发送到信道的发送数据中包含的已知模式数据相同的模式数据,并且获得要通过信道接收的所述模式数据和接收数据之间的相关性。 然后,基于相关值连续地估计信道特性,并根据所述估计结果解调接收数据。 因此,由于可以基于接收数据来估计信道特性,所以即使在由于特性恶化而导致接收数据失真的情况下也能正确地解调数据。

    Data decoding apparatus and method for decoding convolution-coded input data
    5.
    发明授权
    Data decoding apparatus and method for decoding convolution-coded input data 失效
    用于解码卷积编码输入数据的数据解码装置和方法

    公开(公告)号:US06301684B1

    公开(公告)日:2001-10-09

    申请号:US08796070

    申请日:1997-01-30

    IPC分类号: H03M1300

    摘要: In a data decoding apparatus, the Viterbi algorithm is used in an equalizer so that the difference data between state metrics is used as reliability data with respect to the output data so as to provide the reliability data which can accurately represent the likelihood of the output data, whereby it is ensured that efficient decoding of data may be performed based on the reliability data described above.

    摘要翻译: 在数据解码装置中,在均衡器中使用维特比算法,使得状态度量之间的差分数据被用作相对于输出数据的可靠性数据,以便提供可准确地表示输出数据的可能性的可靠性数据 从而确保可以基于上述可靠性数据来执行数据的有效解码。

    Radio receiver apparatus and radio receiving method
    6.
    发明授权
    Radio receiver apparatus and radio receiving method 失效
    无线电接收装置和无线电接收方法

    公开(公告)号:US6038270A

    公开(公告)日:2000-03-14

    申请号:US861166

    申请日:1997-05-21

    IPC分类号: H04L27/22 H04L7/04

    CPC分类号: H04L27/22

    摘要: A radio receiver apparatus and method for decoding a received signal based on a predetermined pattern of synchronization signal which is inserted in a predetermined period comprising demodulating a received signal to a base band signal, decoding the demodulated signal to a data signal, generating a reference signal based on an output of the decoding and detecting a complex correlation value between the data signal and the reference signal wherein the detected synchronizing signal is based on the detected complex correlation value and decoding is based on the detected synchronization signal.

    摘要翻译: 一种无线电接收装置和方法,用于基于在包括将接收信号解调为基带信号的预定周期插入的预定同步信号模式来解码接收信号,将解调信号解码为数据信号,生成参考信号 基于所述解码的输出,并且检测所述数据信号和所述参考信号之间的复相关值,其中所述检测到的同步信号基于所检测到的复相关值,并且基于所检测到的同步信号进行解码。

    Effective bus utilization using multiple bus interface circuits and arbitration logic circuit
    10.
    发明授权
    Effective bus utilization using multiple bus interface circuits and arbitration logic circuit 失效
    有效总线利用率采用多总线接口电路和仲裁逻辑电路

    公开(公告)号:US06959354B2

    公开(公告)日:2005-10-25

    申请号:US09802417

    申请日:2001-03-08

    申请人: Hidekazu Watanabe

    发明人: Hidekazu Watanabe

    CPC分类号: G06F13/4031

    摘要: In one embodiment of the present invention, a bus controller is used in a multi-bus system having first and second buses. The bus controller includes first and second bus interface circuits, a processor interface circuit, and an arbitration logic circuit. The first and second bus interface circuits interface to the first and second buses, respectively. The first bus is accessible to a first processor. The processor interface circuit interfaces to a second processor. The arbitration logic circuit is coupled to the first and second bus interface circuits and the processor interface circuit to arbitrate access requests from the first and second processors.

    摘要翻译: 在本发明的一个实施例中,总线控制器用于具有第一和第二总线的多总线系统中。 总线控制器包括第一和第二总线接口电路,处理器接口电路和仲裁逻辑电路。 第一和第二总线接口电路分别与第一和第二总线接口。 第一个总线可以访问第一个处理器。 处理器接口电路接口到第二处理器。 仲裁逻辑电路耦合到第一和第二总线接口电路和处理器接口电路以仲裁来自第一和第二处理器的访问请求。