公开(公告)号：US08476744B2

公开(公告)日：2013-07-02

申请号：US12978049

申请日：2010-12-23

申请人： Hiekazu Miyairi ,  Shinya Sasagawa ,  Motomu Kurata ,  Asami Tadokoro

发明人： Hiekazu Miyairi ,  Shinya Sasagawa ,  Motomu Kurata ,  Asami Tadokoro

IPC分类号： H01L21/02

CPC分类号： H01L29/78609 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78669 ,  H01L29/78678

摘要： A thin film transistor with favorable electric characteristics is provided. The thin film transistor includes a gate electrode, a gate insulating layer, a semiconductor layer which includes a microcrystalline semiconductor region and an amorphous semiconductor region, an impurity semiconductor layer, a wiring, a first oxide region provided between the microcrystalline semiconductor region and the wiring, and a second oxide region provided between the amorphous semiconductor region and the wiring, wherein a line tangent to the highest inclination of an oxygen profile in the first oxide region (m1) and a line tangent to the highest inclination of an oxygen profile in the second oxide region (m2) satisfy a relation of 1

摘要翻译： 提供具有良好电特性的薄膜晶体管。 薄膜晶体管包括栅电极，栅极绝缘层，包括微晶半导体区域和非晶半导体区域的半导体层，杂质半导体层，布线，设置在微晶半导体区域和布线之间的第一氧化物区域 以及设置在所述非晶半导体区域和所述布线之间的第二氧化物区域，其中与所述第一氧化物区域（m1）中的氧分布的最高倾斜度相切的直线和与所述第一氧化物区域 第二氧化物区域（m2）在半导体层侧满足包括在布线中的元素的轮廓与包含在半导体层中的元素的轮廓的交点的1

公开(公告)号：US20120001178A1

公开(公告)日：2012-01-05

申请号：US12978049

申请日：2010-12-23

申请人： Hiekazu MIYAIRI ,  Shinya Sasagawa ,  Motomu Kurata ,  Asami Tadokoro

发明人： Hiekazu MIYAIRI ,  Shinya Sasagawa ,  Motomu Kurata ,  Asami Tadokoro

IPC分类号： H01L29/786

CPC分类号： H01L29/78609 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78669 ,  H01L29/78678

摘要： A thin film transistor with favorable electric characteristics is provided. The thin film transistor includes a gate electrode, a gate insulating layer, a semiconductor layer which includes a microcrystalline semiconductor region and an amorphous semiconductor region, an impurity semiconductor layer, a wiring, a first oxide region provided between the microcrystalline semiconductor region and the wiring, and a second oxide region provided between the amorphous semiconductor region and the wiring. wherein a line tangent to the highest inclination of an oxygen profile in the first oxide region (m1) and a line tangent to the highest inclination of an oxygen profile in the second oxide region (m2) satisfy a relation of 1

摘要翻译： 提供具有良好电特性的薄膜晶体管。 薄膜晶体管包括栅电极，栅极绝缘层，包括微晶半导体区域和非晶半导体区域的半导体层，杂质半导体层，布线，设置在微晶半导体区域和布线之间的第一氧化物区域 以及设置在非晶半导体区域和布线之间的第二氧化物区域。 其特征在于，与所述第一氧化物区域（m1）中的氧分布的最高倾斜度相切的行和与所述第二氧化物区域（m2）中的氧气剖面的最高倾斜度相切的直线满足1

公开(公告)号：US08436403B2

公开(公告)日：2013-05-07

申请号：US13014081

申请日：2011-01-26

申请人： Shunpei Yamazaki ,  Hiromichi Godo ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Motomu Kurata ,  Mayumi Mikami

发明人： Shunpei Yamazaki ,  Hiromichi Godo ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Motomu Kurata ,  Mayumi Mikami

IPC分类号： H01L21/84

CPC分类号： H01L29/7869 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  Y10T428/24421

摘要： One object is to provide a semiconductor device that includes an oxide semiconductor and is reduced in size with favorable characteristics maintained. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The source electrode or the drain electrode includes a first conductive layer and a second conductive layer having a region extended in a channel length direction from an end face of the first conductive layer. The sidewall insulating layer has a length of a bottom surface in the channel length direction smaller than a length in the channel length direction of the extended region of the second conductive layer and is provided over the extended region.

摘要翻译： 一个目的是提供一种包括氧化物半导体的半导体器件，并且尺寸减小，并保持良好的特性。 半导体器件包括与氧化物半导体层接触的氧化物半导体层，源电极和漏电极，与氧化物半导体层重叠的栅电极; 以及在氧化物半导体层和栅电极之间的栅极绝缘层。 源电极或漏极包括第一导电层和具有从第一导电层的端面在沟道长度方向上延伸的区域的第二导电层。 侧壁绝缘层的沟道长度方向的底面的长度小于第二导电层的延伸区域的沟道长度方向的长度，并且设置在延伸区域上。

公开(公告)号：US07998801B2

公开(公告)日：2011-08-16

申请号：US12424563

申请日：2009-04-16

申请人： Shinya Sasagawa ,  Motomu Kurata ,  Sho Osada

发明人： Shinya Sasagawa ,  Motomu Kurata ,  Sho Osada

IPC分类号： H01L21/00 ,  H01L21/302

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/40 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

摘要： Decrease of the off-state current, increase of the on-state current, and reduction of variations of electrical characteristics. A method for manufacturing a channel-etched inversed staggered thin film transistor includes the following steps: removing, by first dry-etching, a part of a semiconductor layer including an impurity element which imparts one conductivity type, which is exposed from the source and drain electrodes, and partially a part of an amorphous semiconductor layer just below and in contact with the part of the semiconductor layer; removing, by second dry-etching, partially the part of the amorphous semiconductor layer which is exposed by the first dry-etching; and performing plasma treatment on the surface of the part of the amorphous semiconductor layer which is exposed by the second dry-etching so that an altered layer is formed.

摘要翻译： 关闭状态电流的减小，导通电流的增加以及电特性变化的减小。 用于制造通道蚀刻反向交错薄膜晶体管的方法包括以下步骤：通过首先干蚀刻除去包括从源极和漏极暴露的赋予一种导电类型的杂质元素的半导体层的一部分 电极，以及半导体层的正下方并与半导体层的一部分接触的部分非晶半导体层的一部分; 通过第二干法蚀刻部分地除去通过第一干法蚀刻暴露的部分非晶半导体层; 并且通过第二干蚀刻曝光的非晶半导体层的部分的表面进行等离子体处理，从而形成改变的层。

公开(公告)号：US20100096637A1

公开(公告)日：2010-04-22

申请号：US12423829

申请日：2009-04-15

申请人： Shunpei Yamazaki ,  Yuji Egi ,  Shinya Sasagawa ,  Motomu Kurata

发明人： Shunpei Yamazaki ,  Yuji Egi ,  Shinya Sasagawa ,  Motomu Kurata

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/78696

摘要： Off current of a thin film transistor is reduced, and on current of the thin film transistor is increased, and variation in electric characteristics is reduced. As a structure of semiconductor layers which form a channel formation region of a thin film transistor, a first semiconductor layer including a plurality of crystalline regions is provided on a gate insulating layer side; a second semiconductor layer having an amorphous structure is provided on a source region and drain region side; an insulating layer with a thickness small enough to allow carrier travel is provided between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer is in contact with the gate insulating layer. The second semiconductor layer is provided on an opposite side to a face of the first semiconductor layer which is in contact with the gate insulating layer.

摘要翻译： 薄膜晶体管的截止电流减小，薄膜晶体管的导通电流增大，电特性的变化也降低。 作为形成薄膜晶体管的沟道形成区域的半导体层的结构，在栅极绝缘层侧设置包括多个结晶区域的第一半导体层， 在源区和漏区侧设置具有非晶结构的第二半导体层; 在第一半导体层和第二半导体层之间设置具有足够小以允许载流子行进的厚度的绝缘层。 第一半导体层与栅极绝缘层接触。 第二半导体层设置在与栅极绝缘层接触的与第一半导体层的面相反的一侧。

公开(公告)号：US08828844B2

公开(公告)日：2014-09-09

申请号：US12247487

申请日：2008-10-08

申请人： Hideto Ohnuma ,  Tetsuya Kakehata ,  Akihisa Shimomura ,  Shinya Sasagawa ,  Motomu Kurata

发明人： Hideto Ohnuma ,  Tetsuya Kakehata ,  Akihisa Shimomura ,  Shinya Sasagawa ,  Motomu Kurata

IPC分类号： H01L21/46 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/84 ,  H01L21/02 ,  H01L21/302 ,  H01L21/762

CPC分类号： H01L21/76254 ,  H01L21/02532 ,  H01L21/02686 ,  H01L21/268 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/84

摘要： A damaged region is formed by generation of plasma by excitation of a source gas, and by addition of ion species contained in the plasma from one of surfaces of a single crystal semiconductor substrate; an insulating layer is formed over the other surface of the single crystal semiconductor substrate; a supporting substrate is firmly attached to the single crystal semiconductor substrate so as to face the single crystal semiconductor substrate with the insulating layer interposed therebetween; separation is performed at the damaged region into the supporting substrate to which a single crystal semiconductor layer is attached and part of the single crystal semiconductor substrate by heating of the single crystal semiconductor substrate; dry etching is performed on a surface of the single crystal semiconductor layer attached to the supporting substrate; the single crystal semiconductor layer is recrystallized by irradiation of the single crystal semiconductor layer with a laser beam to melt at least part of the single crystal semiconductor layer.

摘要翻译： 通过源气体的激发产生等离子体并通过从单晶半导体衬底的表面之一添加包含在等离子体中的离子种类而形成损伤区域; 在单晶半导体衬底的另一个表面上形成绝缘层; 支撑衬底牢固地附接到单晶半导体衬底，以便在其间插入绝缘层的单晶半导体衬底; 通过加热单晶半导体衬底，在损伤区域处分离成与单晶半导体层相连的支撑衬底和部分单晶半导体衬底; 在附着于支撑基板的单晶半导体层的表面进行干蚀刻， 通过用激光束照射单晶半导体层来使单晶半导体层重结晶，从而熔化至少一部分单晶半导体层。

公开(公告)号：US08383487B2

公开(公告)日：2013-02-26

申请号：US13198171

申请日：2011-08-04

申请人： Hideomi Suzawa ,  Shinya Sasagawa ,  Akihisa Shimomura ,  Junpei Momo ,  Motomu Kurata ,  Taiga Muraoka ,  Kosei Nei

发明人： Hideomi Suzawa ,  Shinya Sasagawa ,  Akihisa Shimomura ,  Junpei Momo ,  Motomu Kurata ,  Taiga Muraoka ,  Kosei Nei

IPC分类号： H01L21/76

CPC分类号： H01L21/76254

摘要： Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.

摘要翻译： 在单晶半导体基板的表面上形成绝缘膜，在单晶半导体基板中通过用离子束照射单晶半导体基板通过绝缘膜形成脆性区域，在绝缘膜上形成接合层， 通过将支撑基板和单晶半导体基板之间的接合层插入到单晶半导体基板的支撑基板上，将单晶半导体基板分割为脆性区域，将单晶半导体基板分离成单晶半导体层， 所述支撑基板对残留在所述单晶半导体层上的所述易碎区域的一部分进行第一干蚀刻处理，对经过所述第一蚀刻处理的所述单晶半导体层的表面进行第二干蚀刻处理， 具有激光的晶体半导体层。

公开(公告)号：US08987727B2

公开(公告)日：2015-03-24

申请号：US13357902

申请日：2012-01-25

申请人： Shinya Sasagawa ,  Motomu Kurata

发明人： Shinya Sasagawa ,  Motomu Kurata

IPC分类号： H01L29/786 ,  H01L21/34 ,  H01L29/417

CPC分类号： H01L29/66969 ,  H01L21/441 ,  H01L29/41733 ,  H01L29/7869

摘要： An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.

摘要翻译： 本发明的目的是提供一种在保持有利特性的同时减小缺陷并实现小型化的半导体器件。 形成半导体层; 在半导体层上形成第一导电层; 使用第一抗蚀剂掩模蚀刻第一导电层以形成具有凹部的第二导电层; 第一抗蚀剂掩模的尺寸减小以形成第二抗蚀剂掩模; 使用第二抗蚀剂掩模蚀刻第二导电层，以形成在周边具有锥形形状的突出部分的源极和漏极; 在源极和漏极上形成栅极绝缘层以与半导体层的一部分接触; 并且栅极电极形成在栅极绝缘层上方并与半导体层重叠的部分。

公开(公告)号：US08723768B2

公开(公告)日：2014-05-13

申请号：US11806071

申请日：2007-05-29

申请人： Yuji Egi ,  Takeshi Nishi ,  Kiyofumi Ogino ,  Shinya Sasagawa ,  Motomu Kurata ,  Hideomi Suzawa

发明人： Yuji Egi ,  Takeshi Nishi ,  Kiyofumi Ogino ,  Shinya Sasagawa ,  Motomu Kurata ,  Hideomi Suzawa

IPC分类号： G09G3/34 ,  G09G3/00 ,  C09K19/00 ,  G03B21/60

CPC分类号： G02B1/118 ,  C09K11/06 ,  C09K2211/1011 ,  C09K2211/1029 ,  C09K2211/185 ,  G02B1/14 ,  G02F1/133502 ,  H01J2211/442 ,  H01L27/3244 ,  H01L51/5281 ,  H05B33/22 ,  Y10T428/10

摘要： The display device includes an anti-reflection film having a plurality of projections over a display screen surface and a protective layer filling a space between the projections. The number of times of incidence of external light entering the display device on the anti-reflection film is increased; therefore, the amount of external light transmitted through the anti-reflection film is increased. Thus, the amount of external light reflected to a viewer side is reduced, and the cause of a reduction in visibility such as reflection can be eliminated. Further, since the plurality of projections is covered with a protective layer, entry of dust can be prevented, and physical strength of the anti-reflection film can be increased.

摘要翻译： 显示装置包括在显示屏表面上具有多个突起的防反射膜和填充突起之间的空间的保护层。 在抗反射膜上进入显示装置的外部光的入射次数增加; 因此，透过防反射膜的外部光量增加。 因此，反射到观察者侧的外部光量减少，并且可以消除诸如反射等可见性的降低的原因。 此外，由于多个突起被保护层覆盖，因此可以防止灰尘进入，并且可以提高抗反射膜的物理强度。

公开(公告)号：US08653513B2

公开(公告)日：2014-02-18

申请号：US13029146

申请日：2011-02-17

申请人： Hideomi Suzawa ,  Shinya Sasagawa ,  Motomu Kurata

发明人： Hideomi Suzawa ,  Shinya Sasagawa ,  Motomu Kurata

IPC分类号： H01L29/78

CPC分类号： H01L29/7869 ,  G11C16/0408 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/1156 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969

摘要： A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode, in which the source electrode or the drain electrode comprises a first conductive layer and a second conductive layer having a region which extends beyond an end portion of the first conductive layer in a channel length direction and which overlaps with part of the gate electrode, in which a sidewall insulating layer is provided over the extended region of the second conductive layer, and in which the sidewall insulating layer comprises a stack of a plurality of different material layers.

摘要翻译： 半导体器件包括与氧化物半导体层接触的氧化物半导体层，源电极和漏电极，与氧化物半导体层重叠的栅电极，以及在氧化物半导体层和栅电极之间的栅极绝缘层， 源电极或漏电极包括第一导电层和第二导电层，第二导电层具有在沟道长度方向上延伸超出第一导电层的端部并且与栅电极的一部分重叠的区域，其中 侧壁绝缘层设置在第二导电层的延伸区域上，并且其中侧壁绝缘层包括多个不同材料层的堆叠。