公开(公告)号：US08700979B2

公开(公告)日：2014-04-15

申请号：US13529390

申请日：2012-06-21

申请人： Hiroaki Arai ,  Shunji Miyazaki ,  Kazuhisa Obuchi

发明人： Hiroaki Arai ,  Shunji Miyazaki ,  Kazuhisa Obuchi

IPC分类号： H03M13/03

CPC分类号： H04L1/0057 ,  H03M13/2981 ,  H03M13/6502 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583 ,  H03M13/6591 ,  H04L1/005 ,  H04L1/0071

摘要： An error correcting code decoding device includes a first decoding circuit, a word-length reduction circuit configured to reduce bit lengths of a first external values corresponding to a plurality of bits obtained after decoding process performed by the first decoding circuit a first predetermined number of times and to reduce bit lengths of words included in word string, and a second decoding circuit configured to decode the bit string by executing a decoding process a second predetermined number of times for calculating second external values and posterior values of the bits included in the bit string in accordance with the word string including the words having the reduced bit lengths using the first external values having the reduced bit lengths as second prior probabilities that corresponding bits among the plurality of bits are the predetermined value.

摘要翻译： 纠错码解码装置包括：第一解码电路，字长缩小电路，被配置为减少与由第一解码电路执行的解码处理之后获得的多个比特相对应的第一外部值的比特长度，第一预定次数 并且减少字串中包含的字的位长度;以及第二解码电路，被配置为通过执行解码处理来对位串进行解码，第二预定次数用于计算第二外部值和包含在位串中的位的后验值 根据包含具有缩减比特长度的字的字串，使用具有缩小比特长度的第一外部值作为第二先验概率，其中多个比特之间的相应比特是预定值。

公开(公告)号：US20130007558A1

公开(公告)日：2013-01-03

申请号：US13529390

申请日：2012-06-21

申请人： Hiroaki Arai ,  Shunji Miyazaki ,  Kazuhisa Obuchi

发明人： Hiroaki Arai ,  Shunji Miyazaki ,  Kazuhisa Obuchi

IPC分类号： H03M13/29 ,  G06F11/10

CPC分类号： H04L1/0057 ,  H03M13/2981 ,  H03M13/6502 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583 ,  H03M13/6591 ,  H04L1/005 ,  H04L1/0071

摘要： An error correcting code decoding device includes a first decoding circuit, a word-length reduction circuit configured to reduce bit lengths of a first external values corresponding to a plurality of bits obtained after decoding process performed by the first decoding circuit a first predetermined number of times and to reduce bit lengths of words included in word string, and a second decoding circuit configured to decode the bit string by executing a decoding process a second predetermined number of times for calculating second external values and posterior values of the bits included in the bit string in accordance with the word string including the words having the reduced bit lengths using the first external values having the reduced bit lengths as second prior probabilities that corresponding bits among the plurality of bits are the predetermined value.

摘要翻译： 纠错码解码装置包括：第一解码电路，字长缩小电路，被配置为减少与由第一解码电路执行的解码处理之后获得的多个比特相对应的第一外部值的比特长度，第一预定次数 并且减少字串中包含的字的位长度;以及第二解码电路，被配置为通过执行解码处理来对位串进行解码，第二预定次数用于计算第二外部值和包含在位串中的位的后验值 根据包含具有缩减比特长度的字的字串，使用具有缩小比特长度的第一外部值作为第二先验概率，其中多个比特之间的相应比特是预定值。

公开(公告)号：US08885618B2

公开(公告)日：2014-11-11

申请号：US12959808

申请日：2010-12-03

申请人： Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

发明人： Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

IPC分类号： H04B7/212 ,  H04N5/225 ,  H04W72/00 ,  H04W36/38 ,  H04W36/00 ,  H04W72/04 ,  H04B7/26 ,  H04W4/02 ,  H04W56/00

CPC分类号： H04W36/38 ,  H04B7/2643 ,  H04B7/2656 ,  H04W4/02 ,  H04W36/0088 ,  H04W56/00 ,  H04W72/04 ,  H04W72/0446

摘要： A wireless communications system including a mobile station MS and base stations BS1 and BS2, wherein one or both of the mobile station MS and the base stations BS1 and BS2 is provided with a unit for notifying information of a frame position with the possibility of transmission of packets based on detection of deterioration of a reception quality and wherein the mobile station MS is provided with a unit for determining a frame position without the possibility of transmission of packets and shifting to a peripheral cell detection mode at this frame position based on information of a frame position with the possibility of transmission of packets, whereby it is possible to shift to a peripheral cell detection mode without lowering the transmission efficiency and without complicating the processing.

摘要翻译： 一种包括移动站MS和基站BS1和BS2的无线通信系统，其中，移动站MS和基站BS1和BS2之一或两者设置有用于通知具有帧位置信息的单元， 基于检测到接收质量恶化的分组，并且其中移动台MS设置有用于确定帧位置的单元，而不具有传输分组的可能性并且基于信息的信息移动到该帧位置处的周边小区检测模式 具有发送分组的可能性的帧位置，由此可以在不降低传输效率的情况下移动到周边小区检测模式，并且不会使处理复杂化。

公开(公告)号：US08464139B2

公开(公告)日：2013-06-11

申请号：US12360477

申请日：2009-01-27

申请人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Norihiro Ikeda

发明人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Norihiro Ikeda

IPC分类号： H03M13/00

CPC分类号： H03M13/2978 ,  H03M13/2975 ,  H03M13/6561 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0066

摘要： A receiving device in a communication system that separates one frame of information bits into plural blocks, performs turbo encoding of the information bits of each block and transmits the result, and decodes the encoded information bits, where the receiving device includes plural decoders number of which is less than the number of blocks per frame. Each decoder performs a decoding process on encoded information bits of each block that have been expressed by likelihood, when a condition for stopping decoding is met, executes the decoding process of encoded information bits of another block for which decoding has not yet been performed. When the condition for stopping decoding has been met for all blocks before the number of times decoding has been performed for each decoder reaches a preset maximum number of repetitions, the decoding results of all the blocks are serially combined, an error detection process is executed.

摘要翻译： 在将一帧信息比特分离成多个块的通信系统中的接收装置，对每个块的信息比特进行Turbo编码，并发送结果，并对编码的信息比特进行解码，其中接收装置包括多个解码器，其数量为 小于每帧的块数。 当满足停止解码的条件时，每个解码器对已经由似然度表示的每个块的编码信息比特执行解码处理，执行尚未执行解码的另一个块的编码信息比特的解码处理。 在对每个解码器执行解码的次数达到预定的最大重复次数之前，当已经满足所有块的停止解码的条件时，所有块的解码结果被串行组合，执行错误检测处理。

公开(公告)号：US08250446B2

公开(公告)日：2012-08-21

申请号：US12071903

申请日：2008-02-27

申请人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Junya Mikami

发明人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Junya Mikami

IPC分类号： G06F11/00

CPC分类号： H03M13/2957 ,  H03M13/3905 ,  H03M13/6577 ,  H03M13/658 ,  H03M13/6588

摘要： A decoder having an element decoding unit generating external information for input data, including an exponent position determining unit, when the external information output from the element decoding unit is input, of information excluding a sign bit from the external information, specifying an exponent that is a bit position where a value different from a sign bit first appears, a mantissa obtaining unit obtaining information of 1-bit or a plurality of bits in a position next to the exponent as a mantissa out of the external information, a storage unit storing the exponent and the mantissa and a restoring unit restoring the external information by reading the exponent and the mantissa stored in the storage unit, wherein the element decoding unit performs iteration decoding based on the restored external information is utilized.

摘要翻译： 一种解码器，具有生成用于输入数据的外部信息的元素解码单元，包括指数位置确定单元，当从元素解码单元输出的外部信息被输入时，从外部信息中排除符号位以外的信息，指定指数为 一个位号，其中与符号位不同的值首先出现，一个尾数获得单元获取位于该指数旁边位置的1位或多个位的信息作为外部信息中的尾数，存储单元存储 指数和尾数，以及恢复单元，通过读取存储在存储单元中的指数和尾数来恢复外部信息，其中元素解码单元基于恢复的外部信息进行迭代解码。

公开(公告)号：US08028223B2

公开(公告)日：2011-09-27

申请号：US12068707

申请日：2008-02-11

申请人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Tetsuya Yano ,  Takashi Dateki ,  Mitsuo Kobayashi ,  Junya Mikami

发明人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Tetsuya Yano ,  Takashi Dateki ,  Mitsuo Kobayashi ,  Junya Mikami

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： H03M13/2957 ,  H03M13/6306 ,  H03M13/635 ,  H03M13/6356 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/1812

摘要： Disclosed is a transmission device which transmits a systematic code obtained by adding parity bits to information bits. When the code rate of the systematic code is a value in a specific range determined by the decoding characteristic in a case where dummy bits are not inserted, a dummy bit insertion portion inserts dummy bits into the information bits and shifts the decoding characteristic, so that the code rate assumes a value outside a specific range determined by the decoding characteristic after shifting. An encoding portion performs systematic encoding of the information bits into which the dummy bits are inserted, and deletes the dummy bits from the results of the encoding to generate a systematic code, and a rate matching portion, performs rate matching such that the size of the systematic code is equal to a size determined by the physical channel transmission rate, and transmits the systematic code.

摘要翻译： 公开了一种发送装置，其发送通过将奇偶校验位加到信息比特而获得的系统代码。 当在未插入虚拟位的情况下，系统代码的码率是由解码特性确定的特定范围内的值时，伪位插入部分将伪位插入信息位并移位解码特性，使得 码率假定在移位之后由解码特性确定的特定范围之外的值。 编码部分对虚拟位被插入的信息比特进行系统编码，并且从编码结果中删除伪比特以产生系统代码，并且速率匹配部分执行速率匹配， 系统码等于由物理信道传输速率确定的大小，并传输系统码。

公开(公告)号：US07860186B2

公开(公告)日：2010-12-28

申请号：US10899068

申请日：2004-07-27

申请人： Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

发明人： Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

IPC分类号： H04L27/36

CPC分类号： H04L27/3488 ,  H03M13/25 ,  H03M13/2957 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0067 ,  H04L1/16

摘要： A transmitting apparatus comprising circuitry operable to generate a plurality of bit sequences using bits included in a first data block and a second data block, circuitry operable to control the plurality of bit sequences to correspond to a signal point on the phase plane, comprising a bit sequence generating unit operable to control the generation of the bit sequences to adjust an occupation rate occupied with predetermined bits included in the first data block to be closer to an occupation rate occupied with predetermined bits included in the second data block in regard to bit positions of the predetermined bits, based on an error tolerance of the respective bit sequences generated resulting from the correspondence to a signal point on the phase plane, and circuitry operable to transmit the signals obtained by multi-level modulations in accordance with each signal point.

摘要翻译： 一种发送装置，包括可操作以使用包括在第一数据块和第二数据块中的比特来生成多个比特序列的电路，所述电路可操作以控制所述多个比特序列以对应于所述相位平面上的信号点，包括比特 序列产生单元，其可操作以控制比特序列的生成，以调整占据第一数据块中包含的预定比特占有率的占有率，以使其相对于第二数据块中包含的预定比特占据的占用率更接近第 基于由与相位平面上的信号点的对应产生的相应比特序列的误差容限，以及可操作以根据每个信号点发送通过多电平调制获得的信号的电路。

公开(公告)号：US07500166B2

公开(公告)日：2009-03-03

申请号：US11152902

申请日：2005-06-15

申请人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Tetsuya Yano

发明人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Tetsuya Yano

IPC分类号： G08C25/02 ,  H04L1/18

CPC分类号： H04L1/1812 ,  H04L1/1819 ,  H04L1/1845 ,  H04L1/201

摘要： A receiver receives data transmitted from a transmitter. The data is stored in a buffer, and a reliability value of the data is computed by a computing unit. A determining unit determines reliability of the data by comparing a reliability value of existing data in the buffer and a reliability value of the data. When the reliability value of the data is higher than a predetermined value, the existing data is combined with the data. Then, an error correcting unit performs error correcting on combined data obtained, and outputs decoded bits. If the combined data includes many errors, retransmission of the data is requested to the transmitter. When the reliability value of the data is lower than the predetermined value, retransmission of data is directly requested without combining the data with the existing data.

摘要翻译： 接收机接收从发射机发送的数据。 数据存储在缓冲器中，数据的可靠性值由计算单元计算。 确定单元通过比较缓冲器中现有数据的可靠性值和数据的可靠性值来确定数据的可靠性。 当数据的可靠性值高于预定值时，将现有数据与数据组合。 然后，错误校正单元对获得的组合数据执行纠错，并输出解码的比特。 如果组合数据包含许多错误，则向发射机请求数据的重传。 当数据的可靠性值低于预定值时，直接请求重发数据而不将数据与现有数据进行组合。

公开(公告)号：US20050180363A1

公开(公告)日：2005-08-18

申请号：US10899068

申请日：2004-07-27

申请人： Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

发明人： Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

IPC分类号： H03M13/25 ,  H03M13/29 ,  H04B7/216 ,  H04J13/00 ,  H04L1/00 ,  H04L1/16 ,  H04L12/66 ,  H04L27/00 ,  H04L27/34

CPC分类号： H04L27/3488 ,  H03M13/25 ,  H03M13/2957 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0067 ,  H04L1/16

摘要： A transmitting apparatus comprising circuitry operable to generate a plurality of bit sequences using bits included in a first data block and a second data block, circuitry operable to control the plurality of bit sequences to correspond to a signal point on the phase plane, comprising a bit sequence generating unit operable to control the generation of the bit sequences to adjust an occupation rate occupied with predetermined bits included in the first data block to be closer to an occupation rate occupied with predetermined bits included in the second data block in regard to bit positions of the predetermined bits, based on an error tolerance of the respective bit sequences generated resulting from the correspondence to a signal point on the phase plane, and circuitry operable to transmit the signals obtained by multi-level modulations in accordance with each signal point.

摘要翻译： 一种发送装置，包括可操作以使用包括在第一数据块和第二数据块中的比特来生成多个比特序列的电路，所述电路可操作以控制所述多个比特序列以对应于所述相位平面上的信号点，所述电路包括位 序列产生单元，其可操作以控制比特序列的生成，以调整占据第一数据块中包含的预定比特占有率的占有率，以使其相对于第二数据块中包含的预定比特占据的占用率更接近第 基于由与相位平面上的信号点的对应产生的相应比特序列的误差容限，以及可操作以根据每个信号点发送通过多电平调制获得的信号的电路。

公开(公告)号：US08406796B2

公开(公告)日：2013-03-26

申请号：US13478621

申请日：2012-05-23

申请人： Kazuhisa Obuchi ,  Tetsuya Yano ,  Shunji Miyazaki ,  Takao Nakagawa

发明人： Kazuhisa Obuchi ,  Tetsuya Yano ,  Shunji Miyazaki ,  Takao Nakagawa

IPC分类号： H04Q7/20

CPC分类号： H04B17/24 ,  H04B17/309 ,  H04L1/0026 ,  H04L1/0027 ,  H04L5/0048 ,  H04L5/0053 ,  Y02D70/122 ,  Y02D70/124

摘要： A method for using a mobile user terminal includes a receiving a signal and a measuring downlink channel quality based on the signal; wherein downlink channel quality information and an uplink pilot signal simultaneously is not transmitted at a period which the mobile user terminal is a state of transmission off in an intermittent fashion.

摘要翻译： 一种使用移动用户终端的方法包括基于该信号接收信号和测量下行链路信道质量; 其中下行链路信道质量信息和上行链路导频信号在移动用户终端是以间歇方式发送的状态的时段内不被发送。