公开(公告)号：US06396888B1

公开(公告)日：2002-05-28

申请号：US09032944

申请日：1998-03-02

申请人： Hiromi Notani ,  Harufusa Kondoh ,  Masahiko Ishiwaki ,  Tsutomu Yoshimura

发明人： Hiromi Notani ,  Harufusa Kondoh ,  Masahiko Ishiwaki ,  Tsutomu Yoshimura

IPC分类号： H04L706

CPC分类号： H03L7/0805 ,  H03L7/0812 ,  H03L7/0891 ,  H04J3/0614 ,  H04L7/0008 ,  H04L7/02 ,  H04L7/04

摘要： A digital data transmission system for transmitting digital data, a frame pulse signal, and a clock using a required minimum number of signal lines and with a simple circuit structure is provided. A signal separation circuit (46) that receives a multiple clock (CKFP) which is a frame pulse signal (FP) multiplexed with a clock (CK) includes a clock recovery circuit (47) for reproducing a recovered clock (RCK) by synchronization with the multiple clock (CKFP) using a synchronization loop, and a frame pulse signal separation circuit (48) for separating a recovered frame pulse signal (RFP) from the multiple clock (CKFP) on the basis of the recovered clock (RCK).

摘要翻译： 提供了一种用于使用所需的最小数量的信号线和简单的电路结构来发送数字数据，帧脉冲信号和时钟的数字数据传输系统。 接收与时钟（CK）复用的帧脉冲信号（FP）的多时钟（CKFP）的信号分离电路（46）包括：时钟恢复电路（47），用于通过与时钟（CK）同步再现再生时钟（RCK） 使用同步环路的多个时钟（CKFP）和基于恢复时钟（RCK）从多个时钟（CKFP）分离恢复的帧脉冲信号（RFP）的帧脉冲信号分离电路（48）。

公开(公告)号：US5874835A

公开(公告)日：1999-02-23

申请号：US719888

申请日：1996-09-25

申请人： Masahiko Ishiwaki ,  Harufusa Kondoh ,  Hiromi Notani

发明人： Masahiko Ishiwaki ,  Harufusa Kondoh ,  Hiromi Notani

IPC分类号： G01R31/317 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/00 ,  H03K19/02

CPC分类号： H03K19/003

摘要： A voltage applying means applies a voltage which determines the logical value of a node to the node, with the signal at the node fixed. Then, an applied voltage removing means removes the voltage applied by the voltage applying means. First and second detecting means detects the logical value of the node before and after the voltage application and removal of the applied voltage. A judging means compares the results of detection of the first and second detecting means to judge whether or not the node is at a high impedance.

摘要翻译： 电压施加装置将确定节点的逻辑值的电压施加到节点，同时节点处的信号被固定。 然后，施加的电压去除装置去除由电压施加装置施加的电压。 第一和第二检测装置检测在施加电压和施加的电压的去除之前和之后节点的逻辑值。 判断装置比较第一和第二检测装置的检测结果，以判断节点是否处于高阻抗。

公开(公告)号：US5883534A

公开(公告)日：1999-03-16

申请号：US747076

申请日：1996-11-08

申请人： Harufusa Kondoh ,  Masahiko Ishiwaki ,  Hiromi Notani

发明人： Harufusa Kondoh ,  Masahiko Ishiwaki ,  Hiromi Notani

IPC分类号： H03K5/125 ,  G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K3/017 ,  H03K3/02 ,  H03K5/00 ,  H03K5/13 ,  H03K5/156 ,  H03K7/08 ,  H03K17/04 ,  H03L7/00 ,  H03L7/081 ,  H03L7/06

CPC分类号： H03L7/0805 ,  H03K5/133 ,  H03K5/1565 ,  H03K7/08 ,  H03L7/0812 ,  H03L7/0814

摘要： The operating speed of an apparatus which operates with a clock is increased by obtaining a clock having a constant duty ratio. The maximum variable delay quantity of a first variable delay circuit 11 is set more than one cycle and less than two cycles of an input clock IN. The delay quantities of the first and second variable delay circuits 11, 12 are decreased with a control signal Vin. In addition, the ratio of the delay quantity of the second variable delay circuit 12 to that of the first variable delay circuit 11 is set to a constant value which is less than 1. A control portion 13 increases and decreases the control signal Vin in such a manner that the phases of an input clock IN and an output clock OUT-A of the first variable delay circuit are coincident with each other. An output clock OUT of the device is set by the output clock OUT-A of the first variable delay circuit, and is reset by an output clock OUT-B of the second variable delay circuit. Consequently, the output clock of the device has the same phase as that of the input clock IN and a constant duty ratio.

摘要翻译： 通过获得具有恒定占空比的时钟来增加用时钟操作的装置的操作速度。 第一可变延迟电路11的最大可变延迟量被设定为输入时钟IN的多于一个周期且小于两个周期。 第一和第二可变延迟电路11,12的延迟量随着控制信号Vin而减小。 此外，第二可变延迟电路12的延迟量与第一可变延迟电路11的延迟量的比率被设置为小于1的常数值。控制部分13增加和减少控制信号Vin 第一可变延迟电路的输入时钟IN和输出时钟OUT-A的相位彼此一致的方式。 器件的输出时钟OUT由第一可变延迟电路的输出时钟OUT-A设置，并由第二可变延迟电路的输出时钟OUT-B复位。 因此，器件的输出时钟具有与输入时钟IN相同的相位和恒定占空比。

公开(公告)号：US5649119A

公开(公告)日：1997-07-15

申请号：US365637

申请日：1994-12-28

申请人： Harufusa Kondoh ,  Hideaki Yamanaka ,  Masahiko Ishiwaki ,  Hiromi Notani

发明人： Harufusa Kondoh ,  Hideaki Yamanaka ,  Masahiko Ishiwaki ,  Hiromi Notani

IPC分类号： H04Q3/00 ,  H04L12/801 ,  H04L12/911 ,  H04L12/931 ,  G06F5/01 ,  G06F13/00

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/3081 ,  H04L49/405 ,  H04L2012/5651

摘要： A plurality of shift memories shifting data are connected in series, destination indicating bits indicative of data destination are stored in destination indicating bit memories corresponding to the shift memories respectively, and a searching circuit is provided adjacent to each of the destination indicating bit memories, which searching circuit searches data by searching the destination indicating bits.

摘要翻译： 多个移位存储器移位数据串联连接，分别指示数据目的地的目的地指示位分别存储在与移位存储器对应的目的地指示位存储器中，并且提供与每个目的地指示位存储器相邻的搜索电路， 搜索电路通过搜索目的地指示位来搜索数据。

公开(公告)号：US06195361B1

公开(公告)日：2001-02-27

申请号：US08957366

申请日：1997-10-24

申请人： Harufusa Kondoh ,  Masahiko Ishiwaki

发明人： Harufusa Kondoh ,  Masahiko Ishiwaki

IPC分类号： H04L1254

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/309 ,  H04L2012/5647 ,  H04L2012/5651 ,  H04Q11/0478

摘要： A network communication device which can discard invalid packets at once is obtained. A plurality of cells received from input lines (IN#1-4) are stored in a shared buffer memory (SBM) and a control portion (CTL) manages tags and addresses. Among the received cells stored in the shared buffer memory (SBM), ones corresponding to discarded management data are not identified. Accordingly, virtually, the received cells in the shared buffer memory (SBM) can be discarded at once.

摘要翻译： 获得可以一次丢弃无效数据包的网络通信设备。 从输入线（IN＃1-4）接收的多个单元被存储在共享缓冲存储器（SBM）中，控制部分（CTL）管理标签和地址。 在存储在共享缓冲存储器（SBM）中的接收到的单元中，不识别对应于丢弃的管理数据的单元。 因此，虚拟地，可以一次丢弃共享缓冲存储器（SBM）中接收到的单元。

公开(公告)号：US5724562A

公开(公告)日：1998-03-03

申请号：US559654

申请日：1995-11-20

申请人： Masahiko Ishiwaki ,  Harufusa Kondoh

发明人： Masahiko Ishiwaki ,  Harufusa Kondoh

IPC分类号： G06F1/06 ,  G06F1/10 ,  G06F1/12 ,  G06F5/06 ,  G06F9/38 ,  G06F1/04

CPC分类号： G06F9/3869

摘要： Flows of data are controlled using an externally supplied clock. A clock-synchronized C-element C1 outputs a sending signal S1 of H level to a data latch DL1 and the subsequent clock-synchronized C-element C2 and outputs an acknowledge signal A1 of H level, in synchronization with a rise of a clock signal CLK1 which is inputted to the clock-synchronized C-element C1 after the clock-synchronized C-element C1 receives a sending signal S0 of H level. Following this, the clock-synchronized C-element C1 causes the acknowledge signal A1 to fall by the next rise of the clock signal CLK1. This latches the data latch DL1. A clock signal CLK2 rises before the clock signal CLK1 falls and rises once again. In synchronization with this rise, the clock-synchronized C-element C2 performs a similar operation. As a result, the precedent clock-synchronized C-element C1 causes the sending signal S1 to fall.

摘要翻译： 使用外部提供的时钟控制数据流。 时钟同步C元件C1将H电平的发送信号S1输出到数据锁存器DL1和随后的时钟同步C元件C2，并与时钟信号的上升同步地输出H电平的确认信号A1 CLK1，其在时钟同步C元件C1接收到H电平的发送信号S0之后被输入到时钟同步的C元件C1。 此后，时钟同步的C元件C1使得确认信号A1下降到时钟信号CLK1的下一个上升沿。 这将锁存数据锁存器DL1。 时钟信号CLK2在时钟信号CLK1下降之前上升，并再次上升。 与此同步，时钟同步的C元件C2执行类似的操作。 结果，先前的时钟同步C元件C1使发送信号S1下降。

公开(公告)号：US06661864B2

公开(公告)日：2003-12-09

申请号：US09929119

申请日：2001-08-15

申请人： Masahiko Ishiwaki

发明人： Masahiko Ishiwaki

IPC分类号： H03K2140

CPC分类号： H03K21/40

摘要： A counter circuit includes a plurality of flip flop circuits (FF circuits) sequentially connected for receiving a common clock signal, and two-input logic gates each having an input connected to an output of a corresponding FF circuit and the other input connected to an output of a common FF circuit, and of which output signal is supplied to an FF circuit positioned at the post stage of the corresponding FF circuit. A booby trap is realized by the two-input logic gates. The value input to each of the FF circuits is determined by logical operation of at most two logical values, so that the counter circuit can be adapted to the increasing frequency of a clock signal CLK. Thus, the counter circuit with the booby trap, capable of performing high-speed operation can be provided.

公开(公告)号：US20070198891A1

公开(公告)日：2007-08-23

申请号：US11609935

申请日：2006-12-13

申请人： Masahiko Ishiwaki

发明人： Masahiko Ishiwaki

IPC分类号： H03M13/00

CPC分类号： H04L1/0061 ,  H03M13/09 ,  H03M13/611

摘要： A communication system comprises a transmitting device and a receiving device. The transmitting device includes means for connecting an addition bit string containing at least one bit 1 to information data, means for generating a CRC code corresponding to a remainder at a polynomial ring on a Galois field defined modulo 2 based on a predetermined generator polynomial of the information data connected with the addition bit string, means for transmitting the information data connected with the CRC code. The receiving device includes means for receiving the data, means for performing an addition of the received data and the addition bit string at a polynomial ring on a Galois field defined modulo 2, means for making a decision as to the presence or absence of a transmission error by determining the remainder at the polynomial ring on the Galois field defined modulo 2 based on the generator polynomial of data.

摘要翻译： 通信系统包括发送设备和接收设备。 发送装置包括用于将包含至少一个比特1的加法比特串连接到信息数据的装置，用于根据预定的生成多项式生成与在多边形环上的余数对应的加洛瓦字段2 与加法位串连接的信息数据，用于发送与CRC码连接的信息数据的装置。 接收装置包括用于接收数据的装置，用于在模2定义的伽罗瓦域上在多项式环上执行接收数据和加法比特串的相加的装置，用于作出关于传输的存在或不存在的决定的装置 通过基于数据的生成多项式确定在加洛瓦域上的多项式环上的余数定义为模2的误差。

公开(公告)号：US20100150567A1

公开(公告)日：2010-06-17

申请号：US12423931

申请日：2009-04-15

申请人： Harufusa Kondo ,  Masahiko Ishiwaki

发明人： Harufusa Kondo ,  Masahiko Ishiwaki

IPC分类号： H04B10/00

CPC分类号： H04B10/40

摘要： An optical transceiver performs an optical transmitting and receiving operation, and has a first memory and an external interface. The external interface receives information from a host device and writes the received information in the first memory. The external interface reads the information from the first memory in response to an external command and transfers externally the read information. The information includes at least one of an operation start date, when the optical transceiver starts the optical transmitting and receiving operation, and an operation termination dates when the optical transceiver terminates the optical transmitting and receiving operation.

摘要翻译： 光收发器执行光发送和接收操作，并且具有第一存储器和外部接口。 外部接口从主机设备接收信息，并将接收的信息写入第一存储器。 外部接口响应于外部命令从第一个存储器读取信息，并从外部读取读取的信息。 该信息包括当光收发器开始光发送和接收操作时的操作开始日期和光收发器终止光发送和接收操作时的操作终止日期。

公开(公告)号：US06725415B2

公开(公告)日：2004-04-20

申请号：US09769413

申请日：2001-01-26

申请人： Masahiko Ishiwaki

发明人： Masahiko Ishiwaki

IPC分类号： H03M1309

CPC分类号： H03M13/091 ,  H03M13/6575

摘要： A hold circuit holds results of processing in an arithmetic circuit collectively receiving four bits from inputs. The inventive arithmetic unit collectively processes an input data string, which has generally been processed bit by bit, by four bits at a time, whereby a CRC arithmetic operation can be speeded up. More preferably, the arithmetic unit can flexibly deal with change of a generating polynominal set in the arithmetic circuit when rendering set data corresponding to the generating polynomial changeable.

摘要翻译： 保持电路保持在从输入共同接收四位的算术电路中的处理结果。 本发明的运算单元一次处理一次一比特地逐个处理的输入数据串，从而可以加快CRC算术运算。 更优选地，当对与生成多项式相对应的设置数据可变时，运算单元可以灵活地处理运算电路中的生成多项式集的变化。