公开(公告)号：US20110283033A1

公开(公告)日：2011-11-17

申请号：US13106788

申请日：2011-05-12

申请人： Hiromichi YAMADA ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro

发明人： Hiromichi YAMADA ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro

IPC分类号： G06F13/24 ,  G06F13/26

CPC分类号： G06F13/24 ,  G06F11/1641 ,  G06F2201/845

摘要： A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.

摘要翻译： 提供了一种缩短CPU的待机时间并提高从性能模式（并行操作）切换到安全模式（主/检测器操作）时的CPU处理效率的计算机系统。 在一个计算机系统中，包括：至少两个CPU; 用于中断CPU的可编程中断控制器; 以及比较器，用于相互比较CPU的输出，分别由CPU执行相互不同的处理的性能模式之间进行切换，以提高CPU的性能和执行相同处理的安全模式，并将比较器的结果进行比较 检测失败可以进行; 可以为每个中断因子设置要中断的CPU; 并且可以针对每个中断因子来设置执行性能模式还是执行安全模式。

公开(公告)号：US20130020978A1

公开(公告)日：2013-01-24

申请号：US13555123

申请日：2012-07-21

申请人： Hiromichi YAMADA ,  Teruaki Sakata ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro ,  Takashi Yasumasu ,  Kazuyoshi Fukuda ,  Kesami Hagiwara

发明人： Hiromichi YAMADA ,  Teruaki Sakata ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro ,  Takashi Yasumasu ,  Kazuyoshi Fukuda ,  Kesami Hagiwara

IPC分类号： H02P7/29 ,  G05B9/02

CPC分类号： G06F11/0754 ,  G06F11/0739 ,  G06F13/00 ,  Y02D10/14

摘要： A microcontroller includes a central processing unit, a PWM signal generation unit which generates a PWM signal according to a generation condition of a PWM signal set by the central processing unit, and a diagnostic unit which inputs the generated PWM signal therein and detects a pulse period and a pulse width, based on the input signal and which determines whether the detected pulse period and pulse width respectively coincide with a pulse period and a pulse width corresponding to the generation condition.

摘要翻译： 微控制器包括中央处理单元，根据由中央处理单元设置的PWM信号的生成条件产生PWM信号的PWM信号生成单元，以及在其中输入生成的PWM信号并检测脉冲周期的诊断单元 以及基于输入信号的脉冲宽度，并且确定检测到的脉冲周期和脉冲宽度是否与脉冲周期和对应于生成条件的脉冲宽度一致。

公开(公告)号：US20100217943A1

公开(公告)日：2010-08-26

申请号：US12706938

申请日：2010-02-17

申请人： Hiromichi YAMADA ,  Yuichi ISHIGURO ,  Nobuyasu KANEKAWA

发明人： Hiromichi YAMADA ,  Yuichi ISHIGURO ,  Nobuyasu KANEKAWA

IPC分类号： G06F12/00

CPC分类号： G06F11/1641 ,  G06F11/1683

摘要： A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.

摘要翻译： 其中相应CPU执行不同应用以提高处理性能的微控制器，并且相应的CPU执行需要安全性并相互比较其结果的应用，以提供写入数据的可靠性。 微控制器具有由第一CPU，第二CPU，第一存储器和第二存储器构成的多个处理系统，并且对于关于预先设定的特定处理的指令处理，执行未复用的对外围模块的写入 两次，并且第一次和第二次的写入数据被相互整理。

公开(公告)号：US20130013881A1

公开(公告)日：2013-01-10

申请号：US13614313

申请日：2012-09-13

申请人： Hiromichi YAMADA ,  Yuichi ISHIGURO ,  Nobuyasu KANEKAWA

发明人： Hiromichi YAMADA ,  Yuichi ISHIGURO ,  Nobuyasu KANEKAWA

IPC分类号： G06F12/00

CPC分类号： G06F11/1641 ,  G06F11/1683

摘要： A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.

摘要翻译： 其中相应CPU执行不同应用以提高处理性能的微控制器，并且相应的CPU执行需要安全性并相互比较其结果的应用，以提供写入数据的可靠性。 微控制器具有由第一CPU，第二CPU，第一存储器和第二存储器构成的多个处理系统，并且对于关于预先设定的特定处理的指令处理，执行未复用的对外围模块的写入 两次，并且第一次和第二次的写入数据被相互整理。

公开(公告)号：US20100131741A1

公开(公告)日：2010-05-27

申请号：US12610422

申请日：2009-11-02

申请人： Hiromichi YAMADA ,  Kotaro Shimamura ,  Kesami Hagiwara ,  Yoshikazu Kiyoshige ,  Yuichi Ishiguro

发明人： Hiromichi YAMADA ,  Kotaro Shimamura ,  Kesami Hagiwara ,  Yoshikazu Kiyoshige ,  Yuichi Ishiguro

IPC分类号： G06F9/30 ,  G06F9/44 ,  G06F9/38

CPC分类号： G06F11/1608 ,  G06F11/004 ,  G06F11/1641 ,  G06F11/1687 ,  G06F2201/83 ,  G06F2201/845

摘要： A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.

摘要翻译： 一种微控制器，其能够通过由多个CPU执行不同的程序来提高处理性能，并且能够通过评估由多个CPU执行的相同处理的结果来检测用于安全需要的处理的异常。 提供了包括CPU和存储器在内的多个处理系统，每个处理系统中的CPU输出的数据分别由用于每个CPU的压缩机压缩和存储。 压缩存储数据由比较器相互比较，当比较结果表示不匹配时，可以检测出异常处理。 即使当多个CPU异步地执行相同的处理时，获得相同处理结果的定时也是不同的，因此可以容易地将它们的处理结果彼此进行比较，因为压缩是由压缩器执行的。 此外，由于在从所有CPU给出比较使能时能够进行比较器的比较，所以可以基于确定多个压缩机的压缩结果的定时来获得比较运算结果。

公开(公告)号：US20080046697A1

公开(公告)日：2008-02-21

申请号：US11868471

申请日：2007-10-06

申请人： Yasuo SUGURE ,  Tomomi ISHIKURA ,  Kazuya HIRAYANAGI ,  Takeshi KATAOKA ,  Seiji TAKEUCHI ,  Hiromichi YAMADA ,  Takanaga YAMAZAKI

发明人： Yasuo SUGURE ,  Tomomi ISHIKURA ,  Kazuya HIRAYANAGI ,  Takeshi KATAOKA ,  Seiji TAKEUCHI ,  Hiromichi YAMADA ,  Takanaga YAMAZAKI

IPC分类号： G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/3012 ,  G06F9/30123

摘要： The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.

摘要翻译： 本发明防止数据处理器由于多个寄存器组的溢出而不期望的操作停止。 状态寄存器包括用于指示多个寄存器组的溢出的溢出标志。 当数据已被保存到寄存器组的所有存储体的状态中发生中断异常时，允许接受的中断异常使用寄存器组，中央处理单元将寄存器组的数据保存到堆栈区域， 反映溢出标志中的溢出状态。 当溢出标志指示溢出状态时，如果从寄存器组到寄存器组的数据恢复被定向，则中央处理单元将数据从堆栈区恢复到寄存器组。