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公开(公告)号：US09323595B2
公开(公告)日：2016-04-26
申请号：US13555123
申请日：2012-07-21
申请人： Hiromichi Yamada , Teruaki Sakata , Nobuyasu Kanekawa , Yuichi Ishiguro , Takashi Yasumasu , Kazuyoshi Fukuda , Kesami Hagiwara
发明人： Hiromichi Yamada , Teruaki Sakata , Nobuyasu Kanekawa , Yuichi Ishiguro , Takashi Yasumasu , Kazuyoshi Fukuda , Kesami Hagiwara
CPC分类号： G06F11/0754 , G06F11/0739 , G06F13/00 , Y02D10/14
摘要： A microcontroller includes a central processing unit, a PWM signal generation unit which generates a PWM signal according to a generation condition of a PWM signal set by the central processing unit, and a diagnostic unit which inputs the generated PWM signal therein and detects a pulse period and a pulse width, based on the input signal and which determines whether the detected pulse period and pulse width respectively coincide with a pulse period and a pulse width corresponding to the generation condition.
摘要翻译： 微控制器包括中央处理单元，根据由中央处理单元设置的PWM信号的生成条件产生PWM信号的PWM信号生成单元，以及在其中输入生成的PWM信号并检测脉冲周期的诊断单元 以及基于输入信号的脉冲宽度，并且确定检测到的脉冲周期和脉冲宽度是否与脉冲周期和对应于生成条件的脉冲宽度一致。
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公开(公告)号：US20140032860A1
公开(公告)日：2014-01-30
申请号：US14110786
申请日：2011-04-21
IPC分类号： G06F12/02
CPC分类号： G06F12/02 , G06F11/1641 , G06F11/167 , G06F11/1687 , G06F2201/845
摘要： First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.
摘要翻译： 从功能模块（2）输出的要写入的第一数据被提供给内置存储器（3）和第一缓冲存储器（11），以及从功能模块（2）输出的要写入的第二数据 ）被提供给内置存储器（3）和第二缓冲存储器（12）。 第一和第二FIFO存储器（13,14）从从第一和第二缓冲存储器（11,12）顺次输出的多个第一和第二输出数据项中选择并存储具有预定数量的输出的数据项，以及 不要选择其他数据项。 比较器（15）将由第一和第二FIFO存储器（13,14）输出的具有预定数量的输出的数据项彼此进行比较。
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公开(公告)号：US09367438B2
公开(公告)日：2016-06-14
申请号：US14110786
申请日：2011-04-21
CPC分类号： G06F12/02 , G06F11/1641 , G06F11/167 , G06F11/1687 , G06F2201/845
摘要： First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.
摘要翻译： 从功能模块（2）输出的要写入的第一数据被提供给内置存储器（3）和第一缓冲存储器（11），以及从功能模块（2）输出的要写入的第二数据 ）被提供给内置存储器（3）和第二缓冲存储器（12）。 第一和第二FIFO存储器（13,14）从从第一和第二缓冲存储器（11,12）顺次输出的多个第一和第二输出数据项中选择并存储具有预定数量的输出的数据项，以及 不要选择其他数据项。 比较器（15）将由第一和第二FIFO存储器（13,14）输出的具有预定数量的输出的数据项彼此进行比较。
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公开(公告)号：US20070180317A1
公开(公告)日：2007-08-02
申请号：US11623441
申请日：2007-01-16
IPC分类号： G06F11/00
CPC分类号： G06F11/1407
摘要： This method is an error correction method such that, when an error is detected in a CPU with pipeline struct, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.
摘要翻译： 该方法是一种错误校正方法，使得当在具有流水线结构的CPU中检测到错误时，通过延迟的寄存器文件来恢复寄存器文件的内容，该延迟寄存器文件保持在之前正确执行的[指令N]的执行完成状态 该错误和执行作为[指令N]的下一条指令的[指令N + 1]的指令的回滚控制。 该方法收集CPU内存在的任意Flip-Flops的奇偶校验结果，并检测出错误。 结果，寄存器文件的内容被恢复到可能由错误导致故障的指令范围之前的指令执行完成状态，并且可以从可能由错误发生故障的指令范围的开始滚转指令 。
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公开(公告)号：US08095825B2
公开(公告)日：2012-01-10
申请号：US11623441
申请日：2007-01-16
CPC分类号： G06F11/1407
摘要： This method is an error correction method such that, when an error is detected in a CPU with pipeline structure, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.
摘要翻译： 该方法是一种错误校正方法，使得当在具有流水线结构的CPU中检测到错误时，寄存器文件的内容由延迟的寄存器文件恢复，该延迟寄存器文件保持在之前正确执行的[指令N]的执行完成状态 该错误和执行作为[指令N]的下一条指令的[指令N + 1]的指令的回滚控制。 该方法收集CPU内存在的任意Flip-Flops的奇偶校验结果，并检测出错误。 结果，寄存器文件的内容被恢复到可能由错误导致故障的指令范围之前的指令执行完成状态，并且可以从可能由错误发生故障的指令范围的开始滚转指令 。
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公开(公告)号：US08046137B2
公开(公告)日：2011-10-25
申请号：US13004414
申请日：2011-01-11
CPC分类号： G06F11/1641 , G06F11/1679 , Y02T10/82
摘要： Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.
摘要翻译： 提供具有相同功能的两个数据处理单元，其中一个用于主机，另一个用于比较，电机单元的控制由主机执行，主数据处理单元和电路单元同步操作 利用第一时钟信号，第二数据处理单元与具有与第一时钟信号相同的周期和不同相位的第二时钟信号同步地操作，并且在比较电路中比较两个数据处理单元的处理结果。 触发器设置在从电路单元到比较数据处理单元和从主数据处理单元到比较器的信号路径的信号路径上，并且第一和第二时钟信号都用于触发器的锁存时钟 根据其输入信号。
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公开(公告)号：US20110106335A1
公开(公告)日：2011-05-05
申请号：US13004414
申请日：2011-01-11
CPC分类号： G06F11/1641 , G06F11/1679 , Y02T10/82
摘要： Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.
摘要翻译： 提供具有相同功能的两个数据处理单元，其中一个用于主机，另一个用于比较，电机单元的控制由主机执行，主数据处理单元和电路单元同步操作 利用第一时钟信号，第二数据处理单元与具有与第一时钟信号相同的周期和不同相位的第二时钟信号同步地操作，并且在比较电路中比较两个数据处理单元的处理结果。 触发器设置在从电路单元到比较数据处理单元和从主数据处理单元到比较器的信号路径的信号路径上，并且第一和第二时钟信号都用于触发器的锁存时钟 根据其输入信号。
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公开(公告)号：US07890233B2
公开(公告)日：2011-02-15
申请号：US12388861
申请日：2009-02-19
CPC分类号： G06F11/1641 , G06F11/1679 , Y02T10/82
摘要： Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.
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公开(公告)号：US20090249271A1
公开(公告)日：2009-10-01
申请号：US12388861
申请日：2009-02-19
CPC分类号： G06F11/1641 , G06F11/1679 , Y02T10/82
摘要： Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.
摘要翻译： 提供具有相同功能的两个数据处理单元，其中一个用于主机，另一个用于比较，电机单元的控制由主机执行，主数据处理单元和电路单元同步操作 利用第一时钟信号，第二数据处理单元与具有与第一时钟信号相同的周期和不同相位的第二时钟信号同步地操作，并且在比较电路中比较两个数据处理单元的处理结果。 触发器设置在从电路单元到比较数据处理单元和从主数据处理单元到比较器的信号路径的信号路径上，并且第一和第二时钟信号都用于触发器的锁存时钟 根据其输入信号。
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10.发明授权Multi-core microcontroller having comparator for checking processing result 有权具有用于检查处理结果的比较器的多核微控制器公开(公告)号：US08433955B2
公开(公告)日：2013-04-30
申请号：US12610422
申请日：2009-11-02
IPC分类号： G06F11/00
CPC分类号： G06F11/1608 , G06F11/004 , G06F11/1641 , G06F11/1687 , G06F2201/83 , G06F2201/845
摘要： A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.
摘要翻译： 一种微控制器，其能够通过由多个CPU执行不同的程序来提高处理性能，并且能够通过评估由多个CPU执行的相同处理的结果来检测用于安全需要的处理的异常。 提供了包括CPU和存储器在内的多个处理系统，每个处理系统中的CPU输出的数据分别由用于每个CPU的压缩机压缩和存储。 压缩存储数据由比较器相互比较，当比较结果表示不匹配时，可以检测出异常处理。 即使当多个CPU异步执行相同的处理时，获得相同处理结果的定时也是不同的，因此压缩机进行压缩，因此可以容易地将它们的处理结果进行比较。 此外，由于在从所有CPU给出比较使能时能够进行比较器的比较，所以可以基于确定多个压缩机的压缩结果的定时来获得比较运算结果。
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