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    Ferroelectric memory device
    6.
    发明授权
    Ferroelectric memory device 有权
    铁电存储器件

    公开(公告)号：US06690599B2

    公开(公告)日：2004-02-10

    申请号：US10026892

    申请日：2001-12-27

    申请人： Kazumasa Hasegawa ,  Eiji Natori ,  Hiromu Miyazawa ,  Junichi Karasawa

    发明人： Kazumasa Hasegawa ,  Eiji Natori ,  Hiromu Miyazawa ,  Junichi Karasawa

    IPC分类号： G11C1122

    CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/101 ,  H01L27/11507 ,  H01L28/55

    摘要： A ferroelectric memory device includes a simple matrix type memory cell array. Provided that the maximum absolute value of a voltage applied between a first signal electrode and a second signal electrode is Vs, polarization P of a ferroelectric capacitor formed of the first signal electrode, the second signal electrode, and ferroelectric layer is within the range of 0.1P(+Vs) P(+⅓Vs) when the applied voltage is changed from −Vs to +⅓Vs.

    摘要翻译： 铁电存储器件包括简单矩阵型存储单元阵列。 假设在第一信号电极和第二信号电极之间施加的电压的最大绝对值为Vs，由第一信号电极，第二信号电极和铁电层形成的铁电电容器的极化P为0.1 当施加的电压从+ Vs变化到-1 / 3Vs时，P（+ Vs） P（+ 1 / 3Vs） -Vs至+ 1 / 3Vs。

    Ferroelectric memory and electronic apparatus
    8.
    发明授权
    Ferroelectric memory and electronic apparatus 失效
    铁电存储器和电子设备

    公开(公告)号：US06930339B2

    公开(公告)日：2005-08-16

    申请号：US10105002

    申请日：2002-03-22

    申请人： Takamitsu Higuchi ,  Setsuya Iwashita ,  Hiromu Miyazawa ,  Kazumasa Hasegawa ,  Eiji Natori

    发明人： Takamitsu Higuchi ,  Setsuya Iwashita ,  Hiromu Miyazawa ,  Kazumasa Hasegawa ,  Eiji Natori

    IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H01L31/119

    CPC分类号： H01L27/105

    摘要： The present invention relates to a ferroelectric memory having a matrix-type memory cell array which has a superior degree of integration, in which the angularity of the ferroelectric layer's hysteresis curve is improved, the production yield is increased and costs are reduced.A ferroelectric memory having improved angularity in the hysteresis curve, and superior memory characteristics, production yield and costs is realized as follows. Namely, a peripheral circuit chip and a memory cell array chip are engaged onto an inexpensive assembly base 300 such as glass or plastic. In memory cell array chip 200, a ferroelectric layer is made to undergo epitaxial growth on to a Si single crystal via a buffer layer and first signal electrode. As a result, a ferroelectric memory can be realized which has improved angularity in the hysteresis curve and superior memory characteristics, production yield, and cost.

    摘要翻译： 本发明涉及一种具有优异的集成度的矩阵式存储单元阵列的铁电存储器，其中提高了铁电层磁滞曲线的角度，提高了生产成本并降低了成本。 具有改善的滞后曲线的角度，优异的存储特性，生产成本和成本的铁电存储器实现如下。 也就是说，外围电路芯片和存储单元阵列芯片被接合到诸如玻璃或塑料的便宜的组装基座300上。 在存储单元阵列芯片200中，使铁电体层通过缓冲层和第一信号电极进行Si单晶的外延生长。 结果，可以实现具有改善的滞后曲线的角度和优异的记忆特性，产量和成本的铁电存储器。

    Ferroelectronic memory and electronic apparatus
    9.
    发明授权
    Ferroelectronic memory and electronic apparatus 失效
    铁电记忆体和电子仪器

    公开(公告)号：US06737690B2

    公开(公告)日：2004-05-18

    申请号：US10105042

    申请日：2002-03-22

    申请人： Takamitsu Higuchi ,  Setsuya Iwashita ,  Hiromu Miyazawa ,  Kazumasa Hasegawa ,  Eiji Natori

    发明人： Takamitsu Higuchi ,  Setsuya Iwashita ,  Hiromu Miyazawa ,  Kazumasa Hasegawa ,  Eiji Natori

    IPC分类号： H01C31119

    CPC分类号： H01L27/11502 ,  H01L21/02197 ,  H01L21/31604 ,  H01L27/105 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L28/60 ,  Y10S257/906

    摘要： The present invention relates to a ferroelectric memory having a matrix-type memory cell array which has an excellent degree of integration, in which the angularity of the ferroelectric layer's hysteresis curve is improved. A ferroelectric memory having both integration and memory characteristics in which the angularity of the ferroelectric layer's hysteresis curve is improved is realized as follows. Namely, a structure is employed in which the memory cell array and the peripheral circuit are in a plane separated from one another, and the ferroelectric layer is made to undergo epitaxial growth on to a Si single crystal via a buffer and the first signal electrodes.

    摘要翻译： 本发明涉及具有优异的集成度的矩阵型存储单元阵列的铁电存储器，其中提高了铁电层磁滞曲线的角度。 如下实现具有集成和存储特性的强电介质存储器，其中铁电层的磁滞曲线的角度得到改善。 也就是说，采用其中存储单元阵列和外围电路处于彼此分离的平面中的结构，并且使铁电层经由缓冲器和第一信号电极经历外延生长到Si单晶。