公开(公告)号：US4757442A

公开(公告)日：1988-07-12

申请号：US874704

申请日：1986-06-16

申请人： Hironobu Sakata

发明人： Hironobu Sakata

IPC分类号： G06F11/14 ,  G06F11/16 ,  G06F11/00 ,  G06F11/30

CPC分类号： G06F11/1658 ,  G06F11/1423 ,  G06F11/1679

摘要： A multi-processing device includes three or more processing systems, each having a processor and a corresponding main memory connected to each other by means of an individual memory bus. The multi-processing device also includes a common memory bus connectable to all the processors and all the main memories of the respective systems, an asynchronism detection circuit connected to the respective processors to produce an asynchronism detection signal indicating which system or systems are in asynchronous state, and a device control circuit responsive to the asynchronism detection signal to send a common memory bus select signal to the main memory of each failed system to change its bus connection from the individual memory bus to the common memory bus. The device control circuit also generates a master designation signal for allowing an arbitrary processor of the normal non-faulty systems to be designated as a master processor, and a copy request signal to the respective processors. The copy request signal causes the master processor to copy the content of the main memory of the normal system to the main memory of each failed system. When the synchronization between the respective systems is established, the device control circuit outputs a restart request signal to the respective processors, thus initiating the execution from a fixed, stored address in a control memory of each processor to enable synchronous starting of all of the processor. The multi-processing device further includes a communication control circuit connected to the common memory bus, thus permitting parallel loading of an initial program to the main memories of the respective systems for achieving recovery in the case where all the systems are asynchronous with each other.

摘要翻译： 多处理装置包括三个或更多个处理系统，每个处理系统具有通过单独的存储器总线相互连接的处理器和对应的主存储器。 多处理装置还包括可连接到所有处理器和各个系统的所有主存储器的公共存储器总线，连接到各个处理器的异步检测电路，以产生指示哪个系统或系统处于异步状态的异步检测信号 以及响应于异步检测信号的设备控制电路，以向每个故障系统的主存储器发送公共存储器总线选择信号，以将其总线连接从单独存储器总线改变为公共存储器总线。 设备控制电路还产生主指定信号，用于允许将正常非故障系统的任意处理器指定为主处理器，并将复制请求信号指定给各个处理器。 复制请求信号使得主处理器将正常系统的主存储器的内容复制到每个故障系统的主存储器。 当建立各个系统之间的同步时，设备控制电路向各个处理器输出重新启动请求信号，从而从每个处理器的控制存储器中的固定的存储地址启动执行，以使所有处理器能够同步启动 。 多处理装置还包括连接到公共存储器总线的通信控制电路，从而允许将初始程序并行加载到各个系统的主存储器，以在所有系统彼此异步的情况下实现恢复。