公开(公告)号：US09029869B2

公开(公告)日：2015-05-12

申请号：US13034264

申请日：2011-02-24

申请人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

发明人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

IPC分类号： H01L29/15 ,  H01L29/739 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7395 ,  H01L29/1033 ,  H01L29/66333

摘要： One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.

摘要翻译： 半导体器件的一个实施例包括：包含第一和第二主表面的碳化硅衬底; 第一主表面上的第一导电型碳化硅层; 在所述第一碳化硅层的表面处的第二导电型第一碳化硅区域; 在第一碳化硅区域的表面处的第一导电型第二碳化硅区域; 在第一碳化硅区域的表面处的第二导电型第三碳化硅区域; 在第一碳化硅区域和第二碳化硅区域之间形成的杂质浓度高于第一碳化硅区域的第二导电型第四碳化硅区域; 栅极绝缘体; 形成在栅极绝缘体上的栅电极; 层间绝缘体; 连接到所述第二碳化硅区域和所述第三碳化硅区域的第一电极; 和在第二主表面上的第二电极。

公开(公告)号：US07947988B2

公开(公告)日：2011-05-24

申请号：US12199848

申请日：2008-08-28

申请人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Johji Nishio

发明人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Johji Nishio

IPC分类号： H01L29/15

CPC分类号： H01L29/7802 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

摘要： A semiconductor device includes an SiC substrate, a first SiC layer of first conductivity provided on the substrate, a second SiC layer of second conductivity provided on the first SiC layer, first and second SiC regions provided in the second SiC layer, facing each other and having the same depth, a third SiC region extending through the first SiC region and reaching the first SiC layer, a gate insulator formed on the first and second SiC regions and the second SiC layer interposed therebetween, a gate electrode formed on the gate insulator, a first contact of first conductivity formed on the second SiC region, a second contact of second conductivity formed on the second SiC region, reaching the second SiC layer through the second SiC region, and a top electrode formed on the first and second contacts, and a bottom electrode formed on a back surface of the substrate.

摘要翻译： 半导体器件包括SiC衬底，设置在衬底上的第一导电性第一SiC层，设置在第一SiC层上的第二导电性第二SiC层，设置在第二SiC层中的第一和第二SiC区域彼此面对， 具有相同深度的第三SiC区域延伸穿过第一SiC区域并到达第一SiC层，形成在第一和第二SiC区域上的第二SiC层和形成在栅极绝缘体上的第二SiC层的栅绝缘体， 形成在第二SiC区域上的第一导电体的第一接触，形成在第二SiC区域上的第二导电体的第二接触通过第二SiC区域到达第二SiC层，以及形成在第一和第二接触体上的顶部电极，以及 形成在基板的背面上的底部电极。

公开(公告)号：US20120056195A1

公开(公告)日：2012-03-08

申请号：US13034264

申请日：2011-02-24

申请人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

发明人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

IPC分类号： H01L29/161

CPC分类号： H01L29/7395 ,  H01L29/1033 ,  H01L29/66333

摘要： One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.

摘要翻译： 半导体器件的一个实施例包括：包含第一和第二主表面的碳化硅衬底; 第一主表面上的第一导电型碳化硅层; 在所述第一碳化硅层的表面处的第二导电型第一碳化硅区域; 在第一碳化硅区域的表面处的第一导电型第二碳化硅区域; 在第一碳化硅区域的表面处的第二导电型第三碳化硅区域; 在第一碳化硅区域和第二碳化硅区域之间形成的杂质浓度高于第一碳化硅区域的第二导电型第四碳化硅区域; 栅极绝缘体; 形成在栅绝缘体上的栅电极; 层间绝缘体; 连接到所述第二碳化硅区域和所述第三碳化硅区域的第一电极; 和在第二主表面上的第二电极。

公开(公告)号：US20110059597A1

公开(公告)日：2011-03-10

申请号：US12716403

申请日：2010-03-03

申请人： Johji Nishio ,  Chiharu Ota ,  Takuma Suzuki ,  Hiroshi Kono ,  Makoto Mizukami ,  Takashi Shinohe

发明人： Johji Nishio ,  Chiharu Ota ,  Takuma Suzuki ,  Hiroshi Kono ,  Makoto Mizukami ,  Takashi Shinohe

IPC分类号： H01L21/20

CPC分类号： H01L29/7802 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02658 ,  H01L21/0495 ,  H01L21/30604 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate; a step of polishing a surface of the silicon carbide semiconductor layer; a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing; a step of performing heat treatment to activate the impurities; a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment; a step of chemically removing the first thermal oxide film; and a step of forming an electrode layer on the silicon carbide semiconductor film.

摘要翻译： 提供了即使当使用包括缺陷的碳化硅半导体时也能够实现大规模半导体器件的高产率的半导体器件的制造方法。 制造半导体器件的方法包括：在碳化硅半导体衬底上外延生长碳化硅半导体层的步骤; 抛光所述碳化硅半导体层的表面的步骤; 在抛光步骤之后将杂质离子注入到碳化硅半导体层中的步骤; 进行热处理以活化杂质的步骤; 在进行热处理的步骤之后，在碳化硅半导体层的表面上形成第一热氧化膜的工序; 化学去除第一热氧化膜的步骤; 以及在所述碳化硅半导体膜上形成电极层的步骤。

公开(公告)号：US08012837B2

公开(公告)日：2011-09-06

申请号：US12716403

申请日：2010-03-03

申请人： Johji Nishio ,  Chiharu Ota ,  Takuma Suzuki ,  Hiroshi Kono ,  Makoto Mizukami ,  Takashi Shinohe

发明人： Johji Nishio ,  Chiharu Ota ,  Takuma Suzuki ,  Hiroshi Kono ,  Makoto Mizukami ,  Takashi Shinohe

IPC分类号： H01L21/336 ,  H01L21/425 ,  H01L21/265

CPC分类号： H01L29/7802 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02658 ,  H01L21/0495 ,  H01L21/30604 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate; a step of polishing a surface of the silicon carbide semiconductor layer; a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing; a step of performing heat treatment to activate the impurities; a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment; a step of chemically removing the first thermal oxide film; and a step of forming an electrode layer on the silicon carbide semiconductor film.

摘要翻译： 提供了即使当使用包括缺陷的碳化硅半导体时也能够实现大规模半导体器件的高产率的半导体器件的制造方法。 制造半导体器件的方法包括：在碳化硅半导体衬底上外延生长碳化硅半导体层的步骤; 抛光所述碳化硅半导体层的表面的步骤; 在抛光步骤之后将杂质离子注入到碳化硅半导体层中的步骤; 进行热处理以活化杂质的步骤; 在进行热处理的步骤之后，在碳化硅半导体层的表面上形成第一热氧化膜的工序; 化学去除第一热氧化膜的步骤; 以及在所述碳化硅半导体膜上形成电极层的步骤。

公开(公告)号：US20090078942A1

公开(公告)日：2009-03-26

申请号：US12199848

申请日：2008-08-28

申请人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Johji Nishio

发明人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Johji Nishio

IPC分类号： H01L29/24 ,  H01L21/04

CPC分类号： H01L29/7802 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

摘要： A semiconductor device includes an SiC substrate, a first SiC layer of first conductivity provided on the substrate, a second SiC layer of second conductivity provided on the first SiC layer, first and second SiC regions provided in the second SiC layer, facing each other and having the same depth, a third SiC region extending through the first SiC region and reaching the first SiC layer, a gate insulator formed on the first and second SiC regions and the second SiC layer interposed therebetween, a gate electrode formed on the gate insulator, a first contact of first conductivity formed on the second SiC region, a second contact of second conductivity formed on the second SiC region, reaching the second SiC layer through the second SiC region, and a top electrode formed on the first and second contacts, and a bottom electrode formed on a back surface of the substrate.

摘要翻译： 半导体器件包括SiC衬底，设置在衬底上的第一导电性第一SiC层，设置在第一SiC层上的第二导电性第二SiC层，设置在第二SiC层中的第一和第二SiC区域彼此面对， 具有相同深度的第三SiC区域延伸穿过第一SiC区域并到达第一SiC层，形成在第一和第二SiC区域上的第二SiC层和形成在栅极绝缘体上的第二SiC层的栅绝缘体， 形成在第二SiC区域上的第一导电体的第一接触，形成在第二SiC区域上的第二导电体的第二接触通过第二SiC区域到达第二SiC层，以及形成在第一和第二接触体上的顶部电极，以及 形成在基板的背面上的底部电极。

公开(公告)号：US07777292B2

公开(公告)日：2010-08-17

申请号：US11821740

申请日：2007-06-25

申请人： Chiharu Ota ,  Johji Nishio ,  Tetsuo Hatakeyama ,  Takashi Shinohe

发明人： Chiharu Ota ,  Johji Nishio ,  Tetsuo Hatakeyama ,  Takashi Shinohe

IPC分类号： H01L31/0312 ,  H01L29/47 ,  H01L29/06 ,  H01L29/872

CPC分类号： H01L29/66712 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/872

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.

摘要翻译： 半导体器件包括具有顶表面和底表面的第一导电类型的半导体衬底，形成在半导体衬底的顶表面上的第一导电类型的半导体层，并且具有活动区域和围绕 有源区域，形成在与有源区域的边缘相邻的边缘终端区域中的第二导电类型的第一半导体区域，第二导电类型的第二半导体区域以片状或网状掩埋在边缘终端区域中 形状基本上与半导体层的表面平行，形成在半导体层的有源区和第一半导体区的一部分上的第一电极和形成在半导体衬底的底表面上的第二电极。

公开(公告)号：US07508045B2

公开(公告)日：2009-03-24

申请号：US11827553

申请日：2007-07-12

申请人： Johji Nishio ,  Takuma Suzuki ,  Chiharu Ota ,  Takashi Shinohe

发明人： Johji Nishio ,  Takuma Suzuki ,  Chiharu Ota ,  Takashi Shinohe

IPC分类号： H01L29/24

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608

摘要： A semiconductor device includes a first-conductivity-type SiC substrate, a first-conductivity-type SiC semiconductor layer formed on the substrate, whose impurity concentration is lower than that of the substrate, a first electrode formed on the semiconductor layer and forming a Schottky junction with the semiconductor layer, a barrier height of the Schottky junction being 1 eV or less, plural second-conductivity-type junction barriers formed to contact the first electrode and each having a depth d1 from an upper surface of the semiconductor layer, a width w, and a space s between adjacent ones of the junction barriers, a second-conductivity-type edge termination region formed outside the junction barriers to contact the first electrode and having a depth d2 from the upper surface of the semiconductor layer, and a second electrode formed on the second surface of the substrate, wherein following relations are satisfied d1/d2≧1, s/d1≦0.6, and s/(w+s)≦0.33.

摘要翻译： 半导体器件包括第一导电型SiC衬底，在衬底上形成的杂质浓度低于衬底的第一导电型SiC半导体层，形成在半导体层上并形成肖特基 与所述半导体层的接合部，所述肖特基结的势垒高度为1eV以下，形成为与所述第一电极接触并且各自具有距所述半导体层的上表面的深度d1的多个第二导电型接合阻挡层， w和相邻的所述结屏障之间的空间，形成在所述结屏障外部的接触所述第一电极并具有距所述半导体层的上表面的深度d2的第二导电型边缘终端区域，以及第二导电类型边缘终端区域 形成在基板的第二表面上的电极，其中满足以下关系：d1 / d2> = 1，s / d1 <= 0.6和s /（w + s）<= 0.33。

公开(公告)号：US20080001159A1

公开(公告)日：2008-01-03

申请号：US11821740

申请日：2007-06-25

申请人： Chiharu Ota ,  Johji Nishio ,  Tetsuo Hatakeyama ,  Takashi Shinohe

发明人： Chiharu Ota ,  Johji Nishio ,  Tetsuo Hatakeyama ,  Takashi Shinohe

IPC分类号： H01L29/04

CPC分类号： H01L29/66712 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/872

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.

摘要翻译： 半导体器件包括具有顶表面和底表面的第一导电类型的半导体衬底，形成在半导体衬底的顶表面上的第一导电类型的半导体层，并且具有活动区域和围绕 有源区域，形成在与有源区域的边缘相邻的边缘终端区域中的第二导电类型的第一半导体区域，第二导电类型的第二半导体区域以片状或网状掩埋在边缘终端区域中 形状基本上与半导体层的表面平行，形成在半导体层的有源区和第一半导体区的一部分上的第一电极和形成在半导体衬底的底表面上的第二电极。

公开(公告)号：US08823148B2

公开(公告)日：2014-09-02

申请号：US13034297

申请日：2011-02-24

申请人： Chiharu Ota ,  Takashi Shinohe ,  Makoto Mizukami ,  Johji Nishio

发明人： Chiharu Ota ,  Takashi Shinohe ,  Makoto Mizukami ,  Johji Nishio

IPC分类号： H01L29/868 ,  H01L29/861 ,  H01L29/66 ,  H01L29/872 ,  H01L29/16

CPC分类号： H01L29/1608 ,  H01L21/02529 ,  H01L21/26513 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor device includes a first-conductivity-type semiconductor substrate; a first-conductivity-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductivity-type second semiconductor layer epitaxially formed on the first semiconductor layer; a second-conductivity-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer; a recess formed in the third semiconductor layer, at least a corner portion of a side face and a bottom surface of the recess being located in the second semiconductor layer; a first electrode in contact with the third semiconductor layer; a second electrode connected to the first electrode and in contact with the second semiconductor layer at the bottom surface of the recess; and a third electrode in contact with a lower surface of the semiconductor substrate.

摘要翻译： 半导体器件包括第一导电型半导体衬底; 形成在半导体衬底上的第一导电型第一半导体层，其杂质浓度低于半导体衬底的杂质浓度; 外延形成在第一半导体层上的第二导电型第二半导体层; 外延形成在第二半导体层上，并且杂质浓度高于第二半导体层的杂质浓度的第二导电型第三半导体层; 形成在所述第三半导体层中的凹部，所述凹部的至少侧面的角部和所述凹部的底面位于所述第二半导体层中; 与第三半导体层接触的第一电极; 连接到所述第一电极并在所述凹部的底表面处与所述第二半导体层接触的第二电极; 以及与半导体衬底的下表面接触的第三电极。