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1.发明授权Frame synchronizing apparatus for quadrature modulation data communication radio receiver 失效正交调制数据通信无线电接收机的帧同步装置
公开(公告)号：US5463627A
公开(公告)日：1995-10-31
申请号：US200592
申请日：1994-02-23
CPC分类号： H04L7/042 , H03L7/085 , H04J3/06 , H04L7/0331 , H04L7/08
摘要： In a frame synchronizing apparatus for a receiver apparatus of a digital data radio communications system in which data are transmitted in frame periods with a fixed data sequence contained each frame, a data correlation circuit obtains successive sequences of values of vector difference between vector values constituting a demodulated digital baseband signal, and successively compares these sequences with a fixed vector difference sequence corresponding to the fixed data sequence, to derive a correlation signal substantially unaffected by any phase rotation in the baseband signal. A frame synchronizing circuit formed as a PLL for generating a frame synchronizing signal, includes a phase comparator which periodically indicates whether a detected phase difference between the correlation signal and frame synchronizing signal is effectively zero, positive or negative, and a counter holding a count value indicating a cumulative phase error between these signals. So long as the detected phase differences are successively effectively zero and the cumulative phase error is sufficiently small, the phase of the frame synchronizing signal is held unchanged, thereby achieving a high degree of phase stability.
摘要翻译： 在数字数据无线电通信系统的接收机装置的帧同步装置中，数据在具有包含每一帧的固定数据序列的帧周期中被发送，数据相关电路获得构成矢量的矢量值之间的向量差的值的连续序列 解调的数字基带信号，并且将这些序列与对应于固定数据序列的固定向量差异序列连续地进行比较，以导出基本上不受基带信号中的任何相位旋转影响的相关信号。 形成为用于产生帧同步信号的PLL的帧同步电路包括周期性地指示相关信号和帧同步信号之间的检测到的相位差是否为零或正的负相位的相位比较器，以及保持计数值的计数器 表示这些信号之间的累积相位误差。 只要检测到的相位差连续有效地为零并且累积相位误差足够小，则帧同步信号的相位保持不变，从而实现高度的相位稳定性。
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2.发明授权Terminal unit apparatus for time division multiplexing access communications system 失效用于时分复用接入通信系统的终端装置
公开(公告)号：US5200977A
公开(公告)日：1993-04-06
申请号：US660054
申请日：1991-02-25
申请人： Hiroshi Ohnishi , Yuuri Yamamoto , Kouei Misaizu
发明人： Hiroshi Ohnishi , Yuuri Yamamoto , Kouei Misaizu
CPC分类号： H03H21/0012 , H04B7/005
摘要： A terminal unit apparatus for a time division multiplexing access radio communications system formed of a base station and a number of terminal units remote from the base station, includes a 2-dimensional adaptive equalizer circuit for equalizing two quadrature-relationship baseband signals which are obtained from a received quadrature digital modulation signal during receiving operation of the terminal unit, and an internal signal source which generates a local oscillator signal for use in demodulating a received signal to obtain these baseband signals. A frequency correction quantity is derived from the average rate of variation in each symbol interval of the ratio of the two main tap coefficients of the 2-dimensional adaptive equalizer circuit, and used to correct the frequency of operation of the internal signal source during both receiving operation and also in transmitting operation, in which the internal signal source provides a carrier signal for modulation. Frequency correction can thereby be achieved that is independent of the effects of multi-path interference to the transmission path upon the received quadrature digital modulation signal.
摘要翻译： 一种用于由基站和远离该基站的多个终端单元形成的时分复用接入无线电通信系统的终端单元装置，包括：二维自适应均衡器电路，用于均衡两个正交关系基带信号， 在终端单元的接收操作期间接收的正交数字调制信号，以及产生用于解调接收信号以获得这些基带信号的本地振荡器信号的内部信号源。 从二维自适应均衡器电路的两个主抽头系数的比率的每个符号间隔的平均变化率导出频率校正量，并且用于在两个接收期间校正内部信号源的操作频率 操作和发送操作，其中内部信号源提供用于调制的载波信号。 从而可以实现与接收到的正交数字调制信号时的多路径干扰对传输路径的影响的频率校正。
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3.发明授权
公开(公告)号：US5555247A
公开(公告)日：1996-09-10
申请号：US515607
申请日：1995-08-16
CPC分类号： H04L7/042 , H03L7/085 , H04J3/06 , H04L7/0331 , H04L7/08
摘要： In a frame synchronizing apparatus for a receiver apparatus of a digital data radio communications system in which data are transmitted in frame periods with a fixed data sequence contained each frame, a data correlation circuit obtains successive sequences of values of vector difference between vector values constituting a demodulated digital baseband signal, and successively compares these sequences with a fixed vector difference sequence corresponding to the fixed data sequence, to derive a correlation signal substantially unaffected by any phase rotation in the baseband signal. A frame synchronizing circuit formed as a PLL for generating a frame synchronizing signal, includes a phase comparator which periodically indicates whether a detected phase difference between the correlation signal and frame synchronizing signal is effectively zero, positive or negative, and a counter holding a count value indicating a cumulative phase error between these signals. So long as the detected phase differences are successively effectively zero and the cumulative phase error is sufficiently small, the phase of the frame synchronizing signal is held unchanged, thereby achieving a high degree of phase stability.
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公开(公告)号：US5150383A
公开(公告)日：1992-09-22
申请号：US665857
申请日：1991-03-07
申请人： Kouei Misaizu , Hiroshi Ohnishi
发明人： Kouei Misaizu , Hiroshi Ohnishi
IPC分类号： H04L27/38
CPC分类号： H04L27/3854
摘要： An asynchronous quadrature demodulator which comprises an asynchronous quadrature detector, a frequency compensating circuit for estimating and compensating a frequency offset between an oscillating frequency of a local oscillator of the asynchronous quadrature detector and a frequency of a received carrier frequency on the basis of correcting signals, a base band complex equalizer for eliminating a transmission-channel distortion due to a multiplex transmission and a data demodulator. Thereby, a reference carrier recovery circuit becomes unnecessary. Thus, the structure of the demodulator can be simplified. Further, the demodulator can stably operate on the transmission channel.
摘要翻译： 一种异步正交解调器，包括异步正交检测器，用于基于校正信号估计和补偿异步正交检测器的本地振荡器的振荡频率与接收载波频率之间的频率偏移的频率补偿电路， 基带复合均衡器，用于消除由多路复用传输引起的传输信道失真和数据解调器。 因此，不需要参考载波恢复电路。 因此，可以简化解调器的结构。 此外，解调器可以在传输信道上稳定地操作。
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公开(公告)号：US5487089A
公开(公告)日：1996-01-23
申请号：US16222
申请日：1993-02-11
申请人： Kouei Misaizu , Shoichiro Honda , Hiroshi Ohnishi
发明人： Kouei Misaizu , Shoichiro Honda , Hiroshi Ohnishi
CPC分类号： H04L25/03133
摘要： An input bit sequence is converted into n-bit parallel symbol signals each representing one symbol. A shift register stores an "m" number of the n-bit parallel symbol signals, shifting the n-bit parallel symbol signals one symbol by one symbol and outputting them. At least one selector is operative for sequentially selecting one of the k-th symbol signal and the (m+1)-k-th symbol signal outputted by the shift register in response to a clock signal, where k equals 1, 2, . . . , (m-1)/2. A sampling counter serves to count pairs of successive clock pulses of the clock signal. An Exclusive-OR circuit executes Exclusive-OR operation between the clock signal and an output signal of the sampling counter. At least one first read-only memory stores data representing portions of predetermined impulse response waveforms, and outputs the data in response to an address signal having higher and lower parts. A second read-only memory stores data representing portions of predetermined impulse response waveforms, and outputs the data in response to an address signal having higher and lower parts. A filter output signal is generated by combining the data output by the first read-only memory and the second read-only memory.
摘要翻译： 输入比特序列被转换成每个表示一个符号的n位并行符号信号。 移位寄存器存储“m”个n位并行符号信号，将n位并行符号信号一个符号一个符号移位并输出。 至少一个选择器用于响应于时钟信号顺序地选择移位寄存器输出的第k个符号信号和（m + 1）-k个符号信号中的一个，其中k等于1,2。 。 。 ，（m-1）/ 2。 采样计数器用于计数时钟信号的连续时钟脉冲对。 异或电路在时钟信号和采样计数器的输出信号之间执行异或运算。 至少一个第一只读存储器存储表示预定脉冲响应波形的部分的数据，并响应于具有较高和较低部分的地址信号输出数据。 第二只读存储器存储表示预定脉冲响应波形的部分的数据，并且响应于具有较高和较低部分的地址信号输出数据。 通过组合由第一只读存储器和第二只读存储器输出的数据来生成滤波器输出信号。
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公开(公告)号：US5426669A
公开(公告)日：1995-06-20
申请号：US077586
申请日：1993-06-17
IPC分类号： H04L7/033 , H04L27/233 , H03D3/18 , H04L27/06
CPC分类号： H04L7/0334 , H04L27/2332
摘要： A quadrature demodulator includes a device for generating first and second reference signals having a quadrature relation with each other. A first demodulating device serves to compare phases of the first reference signal and an input modulated signal to demodulate the input modulated signal into a first binary baseband signal. A second demodulating device serves to compare phases of the second reference signal and the input modulated signal to demodulate the input modulated signal into a second binary baseband signal having a quadrature relation with the first baseband signal. A first counting device operates to count pulses of a clock signal in response to the first baseband signal. A second counting device operates to count pulses of the clock signal in response to the second baseband signal. An address signal is generated in response to the output signals of the first and second counting devices. Data representative of an absolute phase of the input modulated signal is generated in response to the address signal.
摘要翻译： 正交解调器包括用于产生彼此具有正交关系的第一和第二参考信号的装置。 第一解调装置用于比较第一参考信号和输入调制信号的相位，以将输入的调制信号解调为第一二进制基带信号。 第二解调装置用于比较第二参考信号和输入调制信号的相位，以将输入调制信号解调成与第一基带信号具有正交关系的第二二进制基带信号。 第一计数装置用于响应于第一基带信号来计数时钟信号的脉冲。 第二计数装置用于响应于第二基带信号对时钟信号的脉冲进行计数。 响应于第一和第二计数装置的输出信号产生地址信号。 响应于地址信号产生表示输入调制信号的绝对相位的数据。
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公开(公告)号：US5550867A
公开(公告)日：1996-08-27
申请号：US417528
申请日：1995-04-06
IPC分类号： H04L7/033 , H04L27/233 , H04L27/06
CPC分类号： H04L7/0334 , H04L27/2332
摘要： A complex angle converter includes a comparing device. The comparing device operates to derive first difference data representing a difference between predetermined reference data and data represented by a first baseband signal. The comparing device further operates to derive second difference data representing a difference between the predetermined reference data and data represented by a second baseband signal having a quadrature relation with the first baseband signal. The comparing device further operates for comparing absolute values of the first difference data and the second difference data, and for outputting a signal representative of a result of the comparing. The complex angle converter also includes a device serving to group an inversion of a highest bit of the first baseband signal and second highest and lower bits of the second baseband signal into a first set. An additional device serves to group a highest bit of the second baseband signal and second highest and lower bits of the first baseband signal into a second set. A selector operates to select one of the first set and the second set in response to the output signal of the comparing device. A decoder is included for decoding the highest bit of the first baseband signal, the highest bit of the second baseband signal, and the selected one of the first set and the second set into data representing a complex angle.
摘要翻译： 复角度转换器包括比较装置。 比较装置用于导出表示预定参考数据和由第一基带信号表示的数据之间的差异的第一差分数据。 比较装置进一步操作以得出表示预定参考数据与由与第一基带信号具有正交关系的第二基带信号表示的数据之间的差异的第二差分数据。 比较装置还用于比较第一差分数据和第二差分数据的绝对值，并输出表示比较结果的信号。 复角转换器还包括用于将第一基带信号的最高位和第二基带信号的第二高位和低位的反转分组为第一组的装置。 附加设备用于将第二基带信号的最高位和第一基带信号的第二高位和低位分组成第二组。 选择器响应于比较装置的输出信号选择第一组和第二组中的一个。 包括解码器，用于将第一基带信号的最高位，第二基带信号的最高位和第一组和第二组中选定的一个译码成表示复角的数据。
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公开(公告)号：US5703913A
公开(公告)日：1997-12-30
申请号：US684442
申请日：1996-07-19
IPC分类号： H04L7/033 , H04L27/233 , H04L7/00
CPC分类号： H04L7/0334 , H04L27/2332
摘要： A timing signal generator includes a demodulator for an input modulated signal to provide first and second baseband signals having a quadrature relation relative to each other. A converter is used to convert the first and second baseband signals into angle data representing a phase, and a calculator is used to calculate a difference between the phase represented by current angle data and the phase represented by previous angle data, preceding the current angle data by a 1-symbol interval. The calculator outputs data representative of the calculated phase difference. A further converter converts the calculator output data into a binary reference signal responsive to which of predetermined divided regions contains a point corresponding to the calculated difference data. Also included is a generator for generating a symbol timing signal in synchronism with the binary reference signal.
摘要翻译： 定时信号发生器包括用于输入调制信号的解调器，以提供具有彼此正交关系的第一和第二基带信号。 A转换器用于将第一和第二基带信号转换成表示相位的角度数据，并且使用计算器来计算当前角度数据所表示的相位与由当前角度数据之前的先前角度数据表示的相位之间的差 以1符号间隔。 计算器输出表示计算出的相位差的数据。 另外的转换器将计算器输出数据转换成二进制参考信号，响应于哪个预定分割区域包含对应于所计算的差分数据的点。 还包括用于与二进制参考信号同步地产生符号定时信号的发生器。
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公开(公告)号：US20110263908A1
公开(公告)日：2011-10-27
申请号：US13142082
申请日：2009-12-21
申请人： Hiroshi Ohnishi , Hiroshi Danjo
发明人： Hiroshi Ohnishi , Hiroshi Danjo
IPC分类号： C07C27/02
CPC分类号： B01J35/002 , B01J27/16 , B01J31/08 , B01J37/0009 , B01J37/03 , C07C29/1285 , C07C29/88 , C07C31/225
摘要： The present invention provides a method for producing glycerol, including transesterifying an oil-and-fat with an alcohol in the presence of a solid catalyst to obtain a glycerol product liquid and subjecting the glycerol product liquid to adsorption treatment with an ion-exchange resin.
摘要翻译： 本发明提供一种甘油的制造方法，其特征在于，在固体催化剂存在下，使醇与油脂进行酯交换，得到甘油制品液，并用离子交换树脂进行吸附处理。
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公开(公告)号：US06247747B1
公开(公告)日：2001-06-19
申请号：US08817663
申请日：1997-04-22
IPC分类号： B60R2700
CPC分类号： B60J5/0498 , B60J7/1621 , B62D25/2054 , B62D29/045 , B65D88/127
摘要： A panel for a truck having an FRP plate including a woven fabric of reinforcing fiber as a main rigid member, a cargo compartment for a truck using the panel and a truck equipped with the cargo compartment for a truck. The panel and the cargo compartment are light, have sufficient rigidity and strength and excellent in processing and fabricating properties.
摘要翻译： 一种用于具有FRP板的卡车用面板，该FRP板包括作为主刚性构件的增强纤维织物，用于使用该面板的卡车的货舱和配备有用于卡车的货舱的卡车。 面板和货舱是轻的，具有足够的刚度和强度，并且加工和制造性能优异。
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