公开(公告)号：US5670409A

公开(公告)日：1997-09-23

申请号：US511810

申请日：1995-08-07

申请人： Hiroshi Otori ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Masaharu Kubo ,  Atsuyoshi Koike ,  Fumiyuki Kanai

发明人： Hiroshi Otori ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Masaharu Kubo ,  Atsuyoshi Koike ,  Fumiyuki Kanai

IPC分类号： H01L21/304 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10844 ,  H01L27/1052

摘要： A method of fabricating a semiconductor integrated circuit device includes: recessing a second surface portion of a semiconductor substrate; forming elements of a first circuit region capable of performing a first function at a first surface portion of the semiconductor substrate and elements of a second circuit region capable of performing a second function at the recessed second surface portion of the semiconductor substrate, the elements of the first circuit region and those of the second circuit region having relatively small and large sizes as generally measured in a direction perpendicular to the surface portions of the semiconductor substrate, respectively; forming an insulating film to cover the first and second circuit regions, with a result that a level difference is caused between first and second portions of the insulating film on the first and second circuit regions at a relatively lower level and at a relatively higher level, respectively; effecting chemical-mechanical planarization of the insulating film to suppress the level difference in the insulating film for enhancing a focus margin for successive photolithographic steps; and forming wiring conductors on the insulating film with the suppressed level difference, enjoying the enhanced focus margin.

摘要翻译： 一种制造半导体集成电路器件的方法包括：使半导体衬底的第二表面部分凹陷; 形成能够在半导体衬底的第一表面部分处执行第一功能的第一电路区域的元件和能够在半导体衬底的凹入的第二表面部分执行第二功能的第二电路区域的元件， 第一电路区域和第二电路区域的第一电路区域分别具有通常在垂直于半导体衬底的表面部分的方向上测量的相对较小和大的尺寸; 形成绝缘膜以覆盖第一和第二电路区域，结果是在第一和第二电路区域上的绝缘膜的第一和第二部分之间在相对较低的电平和相对较高的水平上产生电平差， 分别; 实现绝缘膜的化学机械平面化，以抑制绝缘膜中的水平差，以提高连续光刻步骤的聚焦余量; 并且在绝缘膜上形成具有抑制的电平差的布线导体，享受增强的聚焦余量。

公开(公告)号：US5347100A

公开(公告)日：1994-09-13

申请号：US857658

申请日：1992-03-26

申请人： Takuya Fukuda ,  Michio Ohue ,  Fumiyuki Kanai ,  Atsuyoshi Koike ,  Katsuaki Saito ,  Kazuo Suzuki

发明人： Takuya Fukuda ,  Michio Ohue ,  Fumiyuki Kanai ,  Atsuyoshi Koike ,  Katsuaki Saito ,  Kazuo Suzuki

IPC分类号： H01L21/768 ,  H01L23/532 ,  B23K9/00 ,  B44C1/22

CPC分类号： H01L21/76801 ,  H01L21/76834 ,  H01L23/5329 ,  H01L2924/0002

摘要： Disclosed are a semiconductor device comprising a semiconductor substrate, a first metal connection layers, a first substrate oxide layer having a specific form, and a second connection pattern layer; a process for producing the device; and a microwave plasma treatment apparatus having gas feed ports in a specific position. The highly reliable semiconductor devices can be produced at a high rate at high yields.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，第一金属连接层，具有特定形式的第一衬底氧化物层和第二连接图案层; 一种生产该装置的方法; 以及具有特定位置的气体供给口的微波等离子体处理装置。 高可靠性的半导体器件可以以高产率高产率生产。

公开(公告)号：US06307217B1

公开(公告)日：2001-10-23

申请号：US08181545

申请日：1994-01-14

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Kyoichiro Asayama ,  Eri Fujita ,  Koichiro Ishibashi ,  Toshiro Aoto ,  Sadayuki Morita ,  Atsuyoshi Koike ,  Masayuki Kojima ,  Yasuo Kiguchi ,  Kazuyuki Suko ,  Fumiyuki Kanai ,  Naotaka Hashimoto ,  Toshiaki Yamanaka

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Kyoichiro Asayama ,  Eri Fujita ,  Koichiro Ishibashi ,  Toshiro Aoto ,  Sadayuki Morita ,  Atsuyoshi Koike ,  Masayuki Kojima ,  Yasuo Kiguchi ,  Kazuyuki Suko ,  Fumiyuki Kanai ,  Naotaka Hashimoto ,  Toshiaki Yamanaka

IPC分类号： H01L2972

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.

摘要翻译： 一种静态随机存取存储器，包括由字线控制的转移MISFET和由驱动器MISFET和负载MISFET构成的触发电路组成的存储单元。 负载MISFET的顶部覆盖有电源电压线，使得层叠结构的电容器元件形成在负载MISFET的栅电极和电源电压线之间。

公开(公告)号：US06512245B2

公开(公告)日：2003-01-28

申请号：US09859045

申请日：2001-05-17

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Kyoichiro Asayama ,  Eri Fujita ,  Koichiro Ishibashi ,  Toshiro Aoto ,  Sadayuki Morita ,  Atsuyoshi Koike ,  Masayuki Kojima ,  Yasuo Kiguchi ,  Kazuyuki Suko ,  Fumiyuki Kanai ,  Naotaka Hashimoto ,  Toshiaki Yamanaka

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Kyoichiro Asayama ,  Eri Fujita ,  Koichiro Ishibashi ,  Toshiro Aoto ,  Sadayuki Morita ,  Atsuyoshi Koike ,  Masayuki Kojima ,  Yasuo Kiguchi ,  Kazuyuki Suko ,  Fumiyuki Kanai ,  Naotaka Hashimoto ,  Toshiaki Yamanaka

IPC分类号： H01L2972

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.

摘要翻译： 一种静态随机存取存储器，包括由字线控制的转移MISFET和由驱动器MISFET和负载MISFET构成的触发电路组成的存储单元。 负载MISFET的顶部覆盖有电源电压线，使得层叠结构的电容器元件形成在负载MISFET的栅电极和电源电压线之间。

公开(公告)号：US20100227474A1

公开(公告)日：2010-09-09

申请号：US12781816

申请日：2010-05-18

申请人： Toshiyuki ARAI ,  Ryousei Kawai ,  Hirofumi Tsuchiyama ,  Fumiyuki Kanai ,  Shinichi Nakabayashi

发明人： Toshiyuki ARAI ,  Ryousei Kawai ,  Hirofumi Tsuchiyama ,  Fumiyuki Kanai ,  Shinichi Nakabayashi

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/0206 ,  H01L21/02068 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76807 ,  H01L21/76819 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/7685

摘要： A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.

摘要翻译： 例如，制造半导体集成电路器件的方法包括抛光晶片边缘的整个区域，使用抛光滚筒抛光晶片边缘的上表面的三个抛光滚筒，研磨滚筒抛光 晶片边缘的中心部分和抛光滚筒抛光晶片边缘的下表面，从而防止导致晶片边缘上的薄膜脱落的障碍物的出现。

公开(公告)号：US07052995B2

公开(公告)日：2006-05-30

申请号：US10176666

申请日：2002-06-24

申请人： Nobuhito Katsumura ,  Yoshiteru Katsumura ,  Hidemi Sato ,  Norihiro Uchida ,  Fumiyuki Kanai

发明人： Nobuhito Katsumura ,  Yoshiteru Katsumura ,  Hidemi Sato ,  Norihiro Uchida ,  Fumiyuki Kanai

IPC分类号： H01L21/302

CPC分类号： H01L21/7684 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76819

摘要： A buried film and a barrier film are polished together using a slurry in which the polishing rate on a substrate material (in particular, silicon oxide), that on a buried-film material (in particular, tungsten) and that on a barrier-film material (in particular, titanium oxide) are substantially equal to one another. This can materialize a buried structure free from any step or steps, at a high polishing rate.

摘要翻译： 将掩埋膜和阻挡膜使用其中衬底材料（特别是氧化硅）上的抛光速率，掩埋膜材料（特别是钨）上的抛光速率和阻挡膜上的抛光速率 材料（特别是氧化钛）基本上彼此相等。 这可以以高抛光速率实现没有任何步骤或步骤的掩埋结构。

公开(公告)号：US5188975A

公开(公告)日：1993-02-23

申请号：US885852

申请日：1992-05-20

申请人： Masayuki Kojima ,  Shinji Nishihara ,  Fumiyuki Kanai

发明人： Masayuki Kojima ,  Shinji Nishihara ,  Fumiyuki Kanai

IPC分类号： H01L23/522 ,  H01L21/311 ,  H01L21/316 ,  H01L21/60 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/31604 ,  H01L21/768 ,  H01L21/76802 ,  H01L2924/0002

摘要： In a semiconductor integrated circuit device having at least three conductor layers, a connection hole for the lower conductor layer and the upper conductor layer can be formed in self-alignment to the intermediate conductor layer after flattening the underlying insulation film for the upper conductor layer and deterioration of the insulation withstand voltage between the upper conductor layer and the intermediate conductor layer can be prevented.

摘要翻译： 在具有至少三个导体层的半导体集成电路器件中，用于下导体层和上导体层的连接孔可以在使用于上导体层的下面的绝缘膜平坦化之后，与中间导体层自对准地形成，以及 可以防止上导体层和中间导体层之间的绝缘耐受电压的劣化。

公开(公告)号：US07250365B2

公开(公告)日：2007-07-31

申请号：US11167253

申请日：2005-06-28

申请人： Toshiyuki Arai ,  Ryousei Kawai ,  Hirofumi Tsuchiyama ,  Fumiyuki Kanai ,  Shinichi Nakabayashi

发明人： Toshiyuki Arai ,  Ryousei Kawai ,  Hirofumi Tsuchiyama ,  Fumiyuki Kanai ,  Shinichi Nakabayashi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/0206 ,  H01L21/02068 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76807 ,  H01L21/76819 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/7685

摘要： A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.

摘要翻译： 例如，制造半导体集成电路器件的方法包括抛光晶片边缘的整个区域，使用抛光滚筒抛光晶片边缘的上表面的三个抛光滚筒，研磨滚筒抛光 晶片边缘的中心部分和抛光滚筒抛光晶片边缘的下表面，从而防止导致晶片边缘上的薄膜脱落的障碍物的出现。

公开(公告)号：US20050250331A1

公开(公告)日：2005-11-10

申请号：US11167253

申请日：2005-06-28

申请人： Toshiyuki Arai ,  Ryousei Kawai ,  Hirofumi Tsuchiyama ,  Fumiyuki Kanai ,  Shinichi Nakabayashi

发明人： Toshiyuki Arai ,  Ryousei Kawai ,  Hirofumi Tsuchiyama ,  Fumiyuki Kanai ,  Shinichi Nakabayashi

IPC分类号： H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L21/30 ,  H01L21/302 ,  H01L21/46 ,  H01L21/461

CPC分类号： H01L21/76843 ,  H01L21/0206 ,  H01L21/02068 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76807 ,  H01L21/76819 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/7685

摘要： A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.

摘要翻译： 例如，制造半导体集成电路器件的方法包括抛光晶片边缘的整个区域，使用抛光滚筒抛光晶片边缘的上表面的三个抛光滚筒，研磨滚筒抛光 晶片边缘的中心部分和抛光滚筒抛光晶片边缘的下表面，从而防止导致晶片边缘上的薄膜脱落的障碍物的出现。

公开(公告)号：US5896150A

公开(公告)日：1999-04-20

申请号：US156909

申请日：1993-11-24

申请人： Atsushi Kobayashi ,  Tatsuo Furuta ,  Fumiyuki Kanai ,  Shinri Sakai ,  Hiroshi Hosokawa

发明人： Atsushi Kobayashi ,  Tatsuo Furuta ,  Fumiyuki Kanai ,  Shinri Sakai ,  Hiroshi Hosokawa

IPC分类号： B41J2/16 ,  B41J2/045 ,  B41J2/04

CPC分类号： B41J2/1629 ,  B41J2/1612 ,  B41J2/1623 ,  B41J2/1631 ,  B41J2/1632 ,  B41J2/1646 ,  B41J2002/14387 ,  B41J2002/14419

摘要： In an ink-jet type recording head including a nozzle plate provided with nozzle openings, a spacer provided with partitions for partitioning pressure generating chambers, ink supply ports and reservoirs, and a plate member sandwiched and fixed together. Displacement of the plate member is produced by piezoelectric vibrators to thereby generate ink droplets. The spacer is formed by anisotropic etching of a silicon single crystal substrate so that the pressure generating chambers, the ink supply ports and the reservoirs are formed as through-holes communicated with each other. Accordingly, etching conditions for the respective through-holes are made equal to each other. In different embodiments, the spacer includes chamfered portions or a plurality of fine planes and steps along which adhesive spreads during assembly of the head. In a further embodiment, the spacer includes different length partitions are between the pressure generating chambers.

摘要翻译： 在包括具有喷嘴开口的喷嘴板的喷墨型记录头中，设置有用于分隔压力产生室，供墨口和储存器的隔板的间隔件和夹在其中并固定在一起的板构件。 板构件的位移由压电振动器产生，从而产生墨滴。 通过硅单晶基板的各向异性蚀刻形成间隔物，使得压力发生室，供墨口和储存器形成为彼此连通的通孔。 因此，使各个通孔的蚀刻条件相等。 在不同的实施例中，间隔件包括倒角部分或多个精细平面和台阶，在组装头部期间粘合剂沿着该平面和台阶延伸。 在另一个实施例中，间隔件包括在压力产生室之间的不同长度的隔板。