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16 条记录 (耗时 0.041 秒)

    Static random access memory
    4.
    发明授权
    Static random access memory 失效
    静态随机存取存储器

    公开(公告)号：US5936909A

    公开(公告)日：1999-08-10

    申请号：US13911

    申请日：1998-01-27

    申请人： Takahiro Sonoda ,  Sadayuki Morita ,  Hirofumi Zushi ,  Haruko Kawachino ,  Hideharu Yahata ,  Kenichi Fukui ,  Tomohiro Nagano ,  Masashige Harada

    发明人： Takahiro Sonoda ,  Sadayuki Morita ,  Hirofumi Zushi ,  Haruko Kawachino ,  Hideharu Yahata ,  Kenichi Fukui ,  Tomohiro Nagano ,  Masashige Harada

    IPC分类号： G11C7/10 ,  G11C11/418 ,  G11C7/00

    CPC分类号： G11C7/1072 ,  G11C11/418 ,  G11C7/1018

    摘要： A static RAM has plurality of memory mats each including a plurality of static memory cells formed in a matrix pattern at points of intersection between a plurality of word lines and a plurality of data lines. upon receipt of an address signal into an address register, an address selection circuit selects a memory cell in one of the memory mats, and connects the selected memory cell to a sense amplifier or a write amplifier furnished corresponding to the memory mat in question. At the same time, an address counter generates an address signal corresponding to the address signal by which one of the memory mats has been selected. When a burst mode is designated by a control signal, the address signal admitted to the address register is used to select a memory cell in a first memory mat. The selected memory cell is connected to the corresponding sense amplifier or write amplifier. Then in accordance with the address signal generated by the address counter, a memory cell in another memory mat is selected and connected to the corresponding sense amplifier or write amplifier.

    摘要翻译： 静态RAM具有多个存储器堆，每个存储器堆包括在多个字线和多个数据线之间的交点处以矩阵模式形成的多个静态存储器单元。 地址选择电路在接收到地址寄存器中的地址信号后，选择存储器垫之一中的存储单元，并将所选择的存储单元连接到与所讨论的存储器衬垫对应的读出放大器或写入放大器。 同时，地址计数器产生与已经选择了一个存储器垫的地址信号对应的地址信号。 当通过控制信号指定突发模式时，允许进入地址寄存器的地址信号用于选择第一存储器存储器中的存储器单元。 所选择的存储单元连接到相应的读出放大器或写放大器。 然后根据地址计数器产生的地址信号，选择另一个存储器存储器中的存储单元并将其连接到相应的读出放大器或写入放大器。

    Synchronous memory unit
    5.
    发明授权
    Synchronous memory unit 失效
    同步存储单元

    公开(公告)号：US5963483A

    公开(公告)日：1999-10-05

    申请号：US133952

    申请日：1998-08-14

    申请人： Hideharu Yahata ,  Kenichi Fukui ,  Yoji Nishio ,  Atsushi Hiraishi ,  Sadayuki Morita

    发明人： Hideharu Yahata ,  Kenichi Fukui ,  Yoji Nishio ,  Atsushi Hiraishi ,  Sadayuki Morita

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1072

    摘要： A synchronous memory unit which includes a plurality of input buffers for receiving address data, a plurality of input latches for holding and outputting address data from in the input buffers according to a clock signal, a plurality of decoders for decoding the address data from the input latches, and a memory cell array having a plurality of memory cells which store and output data signals via bit lines according to the address data decoded by the decoders. Also provided are a sense amplifier for amplifying the output data signals on the bit lines, a selector for selecting one of the amplified output data signals according to the address data decoded by the decoders, and a selector output latch for holding and outputting the amplified output data signal from the selector according to the clock signal. An output latch holds and outputs the amplified output data signal from the selector output latch according to the clock signal. An output buffer receives and outputs the amplified output data signal from the output latch. Each latch includes a first latch for holding and outputting a data signal according to the clock signal, a first switch connected to the first latch for allowing a data signal to pass to the first latch according to the clock signal, and a second latch for holding and outputting a data signal according to the clock signal, and a second switch, connected between the first and second latches, for allowing a data signal to pass from the first latch to the second latch according to the clock signal.

    摘要翻译： 一种同步存储单元，包括用于接收地址数据的多个输入缓冲器，用于根据时钟信号从输入缓冲器中保存和输出地址数据的多个输入锁存器，用于从输入端解码地址数据的多个解码器 锁存器和具有多个存储器单元的存储单元阵列，存储单元根据解码器解码的地址数据经由位线存储和输出数据信号。 还提供了用于放大位线上的输出数据信号的读出放大器，用于根据由解码器解码的地址数据来选择放大的输出数据信号之一的选择器，以及用于保存并输出放大的输出的选择器输出锁存器 来自选择器的数据信号根据时钟信号。 输出锁存器根据时钟信号保存并输出来自选择器输出锁存器的放大输出数据信号。 输出缓冲器从输出锁存器接收并输出放大的输出数据信号。 每个锁存器包括用于根据时钟信号保持和输出数据信号的第一锁存器，连接到第一锁存器的第一开关，用于根据时钟信号使数据信号传送到第一锁存器;以及第二锁存器，用于保持 并根据时钟信号输出数据信号，以及连接在第一和第二锁存器之间的第二开关，用于根据时钟信号允许数据信号从第一锁存器传递到第二锁存器。

    Semiconductor integrated circuit
    6.
    发明申请
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US20050083736A1

    公开(公告)日：2005-04-21

    申请号：US10961134

    申请日：2004-10-12

    申请人： Kenichi Fukui ,  Mitsuru Hiraki ,  Mitsuhiko Okutsu

    发明人： Kenichi Fukui ,  Mitsuru Hiraki ,  Mitsuhiko Okutsu

    IPC分类号： H01L27/04 ,  G05F1/56 ,  G05F3/24 ,  G11C5/14 ,  H01L21/822 ,  G11C16/04

    CPC分类号： G11C5/147 ,  H02M1/32

    摘要： In view of controlling overshoot when the power supply is inputted without increase in the area occupied with a chip in a voltage generating circuit mounted over a semiconductor integrated circuit, an internal voltage generating circuit comprises a voltage generating circuit for generating a second voltage from a first voltage supplied from outside, and an output buffer for generating a third voltage corresponding to the second voltage. The third voltage is used as the operation power supply of the internal circuit. Moreover, a first switch for enabling an output node of the second voltage to become conductive to the predetermined potential and a control circuit for turning ON the first switch for the predetermined period in response to input of the first voltage are also provided. An output terminal of the output buffer is not clamped but an output of the voltage generating circuit in the preceding stage is clamped to the predetermined voltage. The transistor of the first switch for clamping the voltage may be remarkably reduced in size in comparison with an output transistor of the output buffer. Accordingly, the area occupied by the chip is not enlarged.

    摘要翻译： 考虑到在输入电源时控制过冲，而不增加安装在半导体集成电路上的电压产生电路中的芯片占用的面积，内部电压产生电路包括电压产生电路，用于从第一 从外部提供的电压，以及用于产生对应于第二电压的第三电压的输出缓冲器。 第三电压用作内部电路的工作电源。 此外，还提供了用于使得第二电压的输出节点能够导通到预定电位的第一开关和用于响应于第一电压的输入而使第一开关接通预定时段的控制电路。 输出缓冲器的输出端子不被钳位，而前一级的电压产生电路的输出被钳位到预定电压。 与输出缓冲器的输出晶体管相比，用于钳位电压的第一开关的晶体管的尺寸可以显着减小。 因此，芯片所占据的面积不会扩大。

    Semiconductor integrated circuit device
    7.
    发明授权
    Semiconductor integrated circuit device 有权

    公开(公告)号：US06584031B2

    公开(公告)日：2003-06-24

    申请号：US10107139

    申请日：2002-03-28

    申请人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

    发明人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

    IPC分类号： G11C700

    CPC分类号： G11C5/147

    摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.

    SEMICONDUCTOR INTEGRATED CIRCUIT
    8.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路

    公开(公告)号：US20090039846A1

    公开(公告)日：2009-02-12

    申请号：US12251519

    申请日：2008-10-15

    申请人： Takayasu Ito ,  Mitsuru Hiraki ,  Satoshi Baba ,  Kenichi Fukui

    发明人： Takayasu Ito ,  Mitsuru Hiraki ,  Satoshi Baba ,  Kenichi Fukui

    IPC分类号： G05F1/565

    CPC分类号： H03K17/22 ,  H03K17/163

    摘要： In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ΔV between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.

    摘要翻译： 为了高精度地设定在接通电源时在功率开关电路中流动的冲击电流的值，LSI的内部电路Int_Cir从输出晶体管MP1被提供内部源极电压Vint 的稳压器VReg的电源开关电路PSWC。 电源开关电路PSWC包括控制电路CNTRLR和启动电路STC。 在电源的“接通”之后的初始时段期间，启动电路STC控制输出晶体管MP1并降低初级冲击电流，使得输出晶体管MP1的输出电流Isup可以表示近似恒定的增量 随着时间的流逝。 由负载电容C的内部电流电压与由启动电路STC控制的输出电流Isup和来自调节器VReg的当前电压Vint之间的差值DeltaV设定在预定极限内，以减小二次冲击电流 。

    Semiconductor integrated circuit
    9.
    发明申请
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US20070145922A1

    公开(公告)日：2007-06-28

    申请号：US11606031

    申请日：2006-11-30

    申请人： Takayasu Ito ,  Mitsuru Hiraki ,  Satoshi Baba ,  Kenichi Fukui

    发明人： Takayasu Ito ,  Mitsuru Hiraki ,  Satoshi Baba ,  Kenichi Fukui

    IPC分类号： H02P3/00

    CPC分类号： H03K17/22 ,  H03K17/163

    摘要： In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ΔV between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.

    摘要翻译： 为了高精度地设置在接通电源时在功率开关电路中流动的冲击电流的值，LSI的内部电路Int_Cir从输出晶体管MP提供内部源极电压Vint 电源开关电路PSWC的调节器VReg中的1个。 电源开关电路PSWC包括控制电路CNTRLR和启动电路STC。 在电源的“接通”之后的初始阶段期间，启动电路STC控制输出晶体管MP1并减小初级冲击电流，使得输出晶体管MP 1的输出电流Isup可以表示大约 随着时间的推移不断增加。 由负载电容C的内部电流电压与由启动电路STC控制的输出电流Isup和来自调节器VReg的当前电压Vint之间的差值DeltaV设定在预定极限内，以减小二次冲击电流 。

    Semiconductor integrated circuit device
    10.
    发明授权
    Semiconductor integrated circuit device 有权

    公开(公告)号：US06288967B1

    公开(公告)日：2001-09-11

    申请号：US09742078

    申请日：2000-12-22

    申请人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

    发明人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

    IPC分类号： G11C700

    摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.