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14 条记录 (耗时 0.073 秒)

    Static random access memory
    4.
    发明授权
    Static random access memory 失效
    静态随机存取存储器

    公开(公告)号：US5936909A

    公开(公告)日：1999-08-10

    申请号：US13911

    申请日：1998-01-27

    申请人： Takahiro Sonoda ,  Sadayuki Morita ,  Hirofumi Zushi ,  Haruko Kawachino ,  Hideharu Yahata ,  Kenichi Fukui ,  Tomohiro Nagano ,  Masashige Harada

    发明人： Takahiro Sonoda ,  Sadayuki Morita ,  Hirofumi Zushi ,  Haruko Kawachino ,  Hideharu Yahata ,  Kenichi Fukui ,  Tomohiro Nagano ,  Masashige Harada

    IPC分类号： G11C7/10 ,  G11C11/418 ,  G11C7/00

    CPC分类号： G11C7/1072 ,  G11C11/418 ,  G11C7/1018

    摘要： A static RAM has plurality of memory mats each including a plurality of static memory cells formed in a matrix pattern at points of intersection between a plurality of word lines and a plurality of data lines. upon receipt of an address signal into an address register, an address selection circuit selects a memory cell in one of the memory mats, and connects the selected memory cell to a sense amplifier or a write amplifier furnished corresponding to the memory mat in question. At the same time, an address counter generates an address signal corresponding to the address signal by which one of the memory mats has been selected. When a burst mode is designated by a control signal, the address signal admitted to the address register is used to select a memory cell in a first memory mat. The selected memory cell is connected to the corresponding sense amplifier or write amplifier. Then in accordance with the address signal generated by the address counter, a memory cell in another memory mat is selected and connected to the corresponding sense amplifier or write amplifier.

    摘要翻译： 静态RAM具有多个存储器堆，每个存储器堆包括在多个字线和多个数据线之间的交点处以矩阵模式形成的多个静态存储器单元。 地址选择电路在接收到地址寄存器中的地址信号后，选择存储器垫之一中的存储单元，并将所选择的存储单元连接到与所讨论的存储器衬垫对应的读出放大器或写入放大器。 同时，地址计数器产生与已经选择了一个存储器垫的地址信号对应的地址信号。 当通过控制信号指定突发模式时，允许进入地址寄存器的地址信号用于选择第一存储器存储器中的存储器单元。 所选择的存储单元连接到相应的读出放大器或写放大器。 然后根据地址计数器产生的地址信号，选择另一个存储器存储器中的存储单元并将其连接到相应的读出放大器或写入放大器。

    Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device
    5.
    发明授权
    Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device 失效
    半导体晶片，半导体芯片和半导体器件的制造方法

    公开(公告)号：US06885599B2

    公开(公告)日：2005-04-26

    申请号：US10764539

    申请日：2004-01-27

    申请人： Yoshikazu Saitoh ,  Sadayuki Morita ,  Takahiro Sonoda

    发明人： Yoshikazu Saitoh ,  Sadayuki Morita ,  Takahiro Sonoda

    IPC分类号： G01R31/30 ,  G01R31/28 ,  G11C29/00 ,  G11C29/48 ,  H01L21/66 ,  G11C7/00

    CPC分类号： G11C29/48

    摘要： By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A packaging structure in which, for example, a volatile memory chip and a nonvolatile memory chip are formed is assembled in accordance with a production scheme in which burn-in of each memory chip is performed while still under the state of a semiconductor wafer, and by forming the packaged structure using the good volatile memory chip subjected to burn-in and likewise, also, the nonvolatile memory chip. At this burn-in, contact check is performed by bringing a needle, provided in a burn-in board, into contact with, for example, six test-only signal terminals of a test circuit formed on each semiconductor chip.

    摘要翻译： 通过在老化期间使用少量的针和接触端子，在每个针与每个半导体芯片中提供的每个端子之间进行电接触检查，从而可以提高组装产品的产量。 根据其中形成有易失性存储器芯片和非易失性存储器芯片的封装结构，根据在半导体晶片的状态下执行每个存储芯片的老化的生产方案，并且 通过使用经过老化的良好易失性存储器芯片以及类似地，非易失性存储器芯片形成封装结构。 在该老化期间，通过将设置在老化板中的针与例如在每个半导体芯片上形成的测试电路的六个测试信号端子接触来进行接触检查。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06680869B2

    公开(公告)日：2004-01-20

    申请号：US10120447

    申请日：2002-04-12

    申请人： Takahiro Sonoda ,  Takeshi Sakata ,  Sadayuki Morita ,  Yoshinobu Nakagome ,  Haruko Tadokoro ,  Osamu Nagashima

    发明人： Takahiro Sonoda ,  Takeshi Sakata ,  Sadayuki Morita ,  Yoshinobu Nakagome ,  Haruko Tadokoro ,  Osamu Nagashima

    IPC分类号： G11C700

    CPC分类号： G11C7/1087 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/12

    摘要： A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.

    摘要翻译： DDR配置的半导体存储器件提高了毛刺抗扰性，并且提供了使用的便利。 它是一种动态类型的RAM，其内部电路与时钟信号同步地被控制; 提供了一种输入电路，其中在写入操作时输入的第二时钟信号用于将响应于该信号串行输入的多个写数据写入多个第一锁存电路，并且所述第一时钟信号用于采取 写入第一锁存电路的数据进入第二锁存电路，以将它们传送到输入/输出数据总线; 提供逻辑电路，以根据第一时钟信号和第二时钟信号的逻辑屏蔽在第二时钟信号结束时产生的任何噪声，并产生第三时钟信号并将其提供给第一锁存电路 其将写数据输出到至少第二锁存电路的输入。

    Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device
    7.
    发明授权
    Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device 失效
    半导体晶片，半导体芯片和半导体器件的制造方法

    公开(公告)号：US06711075B2

    公开(公告)日：2004-03-23

    申请号：US09906060

    申请日：2001-07-17

    申请人： Yoshikazu Saitoh ,  Sadayuki Morita ,  Takahiro Sonoda

    发明人： Yoshikazu Saitoh ,  Sadayuki Morita ,  Takahiro Sonoda

    IPC分类号： G11C700

    CPC分类号： G11C29/48

    摘要： By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A packaging structure in which, for example, a volatile memory chip and a nonvolatile memory chip are formed is assembled in accordance with a production scheme in which burn-in of each memory chip is performed while still under the state of a semiconductor wafer, and by forming the packaged structure using the good volatile memory chip subjected to burn-in and likewise, also, the nonvolatile memory chip. At this burn-in, contact check is performed by bringing a needle, provided in a burn-in board, into contact with, for example, six test-only signal terminals of a test circuit formed on each semiconductor chip.

    摘要翻译： 通过在老化期间使用少量的针和接触端子，在每个针与每个半导体芯片中提供的每个端子之间进行电接触检查，从而可以提高组装产品的产量。 根据其中形成有易失性存储器芯片和非易失性存储器芯片的封装结构，根据在半导体晶片的状态下执行每个存储芯片的老化的生产方案，并且 通过使用经过老化的良好易失性存储器芯片以及类似地，非易失性存储器芯片形成封装结构。 在该老化期间，通过将设置在老化板中的针与例如在每个半导体芯片上形成的测试电路的六个测试信号端子接触来进行接触检查。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06335901B1

    公开(公告)日：2002-01-01

    申请号：US09531467

    申请日：2000-03-20

    申请人： Sadayuki Morita ,  Takeshi Sakata ,  Satoru Hanzawa ,  Takahiro Sonoda ,  Haruko Tadokoro ,  Hiroshi Ichikawa ,  Osamu Nagashima

    发明人： Sadayuki Morita ,  Takeshi Sakata ,  Satoru Hanzawa ,  Takahiro Sonoda ,  Haruko Tadokoro ,  Hiroshi Ichikawa ,  Osamu Nagashima

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.

    摘要翻译： 响应于外部端子（OPT）的第一状态，SDRAM将其操作模式选择为SDR模式，从而释放已经从存储器读出的数据，以响应于由时钟产生的时钟信号 再生电路具有响应于外部端子（OPT）的第二状态而比较电路的输入和输出的相位或选择为DDR模式的功能，从而释放从 响应于与外部时钟信号同步的由时钟信号发生电路产生的时钟信号，存储器垫。

    Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device
    9.
    发明申请
    Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device 审中-公开

    公开(公告)号：US20050185485A1

    公开(公告)日：2005-08-25

    申请号：US11113147

    申请日：2005-04-25

    申请人： Yoshikazu Saitoh ,  Sadayuki Morita ,  Takahiro Sonoda

    发明人： Yoshikazu Saitoh ,  Sadayuki Morita ,  Takahiro Sonoda

    IPC分类号： G01R31/30 ,  G01R31/28 ,  G11C29/00 ,  G11C29/48 ,  H01L21/66 ,  G11C7/00

    CPC分类号： G11C29/48

    摘要： By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A packaging structure in which, for example, a volatile memory chip and a nonvolatile memory chip are formed is assembled in accordance with a production scheme in which burn-in of each memory chip is performed while still under the state of a semiconductor wafer, and by forming the packaged structure using the good volatile memory chip subjected to burn-in and likewise, also, the nonvolatile memory chip. At this burn-in, contact check is performed by bringing a needle, provided in a burn-in board, into contact with, for example, six test-only signal terminals of a test circuit formed on each semiconductor chip.

    Semiconductor device
    10.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06754133B2

    公开(公告)日：2004-06-22

    申请号：US10231286

    申请日：2002-08-30

    申请人： Sadayuki Morita ,  Takeshi Sakata ,  Satoru Hanzawa ,  Takahiro Sonoda ,  Haruko Tadokoro ,  Hiroshi Ichikawa ,  Osamu Nagashima

    发明人： Sadayuki Morita ,  Takeshi Sakata ,  Satoru Hanzawa ,  Takahiro Sonoda ,  Haruko Tadokoro ,  Hiroshi Ichikawa ,  Osamu Nagashima

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： A Synchronous Dynamic Random Access Memory (SDRAM) has its operation mode selected to be the Single Data Rate (SDR) mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the Double Data Rate (DDR) mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock. In the SDR mode, data are transferred via data lines in SDRAM unidirectionally and in the DDR mode, data are transferred via the data lines bidirectionally.

    摘要翻译： 响应于外部终端（OPT）的第一状态，同步动态随机存取存储器（SDRAM）的操作模式选择为单数据速率（SDR）模式，从而释放从存储器中读出的数据 响应于具有比较电路的输入和输出的相位或者被选择为双倍数据速率（DDR）模式的功能的时钟再生电路产生的时钟信号响应于第二状态 外部端子（OPT），从而释放已经从存储器垫读出的数据，响应于与外部时钟同步的时钟信号产生电路产生的时钟信号。 在SDR模式下，数据通过SDRAM中的数据线单向传输，在DDR模式下，数据通过数据线双向传输。