公开(公告)号：US4687954A

公开(公告)日：1987-08-18

申请号：US708508

申请日：1985-03-05

申请人： Hiroshi Yasuda ,  Kiyofumi Ochii ,  Fujio Masuoka

发明人： Hiroshi Yasuda ,  Kiyofumi Ochii ,  Fujio Masuoka

IPC分类号： H03K3/3565 ,  H03K3/356

CPC分类号： H03K3/3565

摘要： A transistor circuit with hysteresis operation, which is formed with a detector part and selector part. The detector part detects a change in the level of an input signal according to one of first and second threshold levels, and generates an output signal having a level corresponding to the input signal. The level of the input signal is changed between a first level and a second level which is lower than the first level. The first and second threshold levels fall within a range defined between the first and second levels. The selector part selects one of the first and second threshold levels in accordance with the level of the output signal, and applies the selected one threshold level to the detector part.

摘要翻译： 具有迟滞操作的晶体管电路，其形成有检测器部​​分和选择器部分。 检测器部分根据第一和第二阈值电平之一检测输入信号电平的变化，并产生具有与输入信号对应的电平的输出信号。 输入信号的电平在低于第一电平的第一电平和第二电平之间改变。 第一和第二阈值水平落在第一和第二水平之间限定的范围内。 选择器部分根据输出信号的电平来选择第一和第二阈值电平中的一个，并将所选择的一个阈值电平施加到检测器部分。

公开(公告)号：US4570091A

公开(公告)日：1986-02-11

申请号：US592717

申请日：1984-03-23

申请人： Hiroshi Yasuda ,  Kiyofumi Ochii

发明人： Hiroshi Yasuda ,  Kiyofumi Ochii

IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/409 ,  H03K19/017 ,  H03K19/0175 ,  H03K17/04 ,  H03K5/153 ,  H03K17/687 ,  H03K19/096

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  H03K19/01707 ,  H03K19/01721

摘要： An output buffer circuit has a data input terminal which receives logic data, load and drive transistors, a driver for selectively turning on the transistors in accordance with the logic value of the logic data, a data output terminal which is connected to a power source terminal of the VDD level through a current path of the load transistor and is grounded through a current path of the drive transistor, and a capacitor connected as a load to the data output terminal. The output buffer circuit further has a transistion detector circuit for generating a pulse signal in response to a change in level of each of address signals, and a preset circuit for supplying, in response to the pulse signal, a charge or discharge current to the capacitor while a voltage at the data output terminal is not at the VDD/2 level.

摘要翻译： 输出缓冲电路具有接收逻辑数据的数据输入端子，负载和驱动晶体管，根据逻辑数据的逻辑值有选择地导通晶体管的驱动器，连接到电源端子的数据输出端子 的VDD电平通过负载晶体管的电流路径并通过驱动晶体管的电流路径接地，并且将电容器作为负载连接到数据输出端子。 输出缓冲器电路还具有用于响应于每个地址信号的电平变化而产生脉冲信号的转移检测器电路，以及用于响应脉冲信号向电容器提供充电或放电电流的预设电路 而数据输出端子的电压不为VDD / 2电平。

公开(公告)号：US4490697A

公开(公告)日：1984-12-25

申请号：US386091

申请日：1982-06-07

申请人： Hiroshi Yasuda ,  Kiyofumi Ochii

发明人： Hiroshi Yasuda ,  Kiyofumi Ochii

IPC分类号： G11C11/41 ,  G11C5/06 ,  G11C11/407 ,  H01L23/522 ,  H03H7/30 ,  H01P9/00

CPC分类号： G11C5/063 ,  H01L23/5222 ,  H01L2924/0002

摘要： There is provided a signal propagating device for receiving an input signal at an input end thereof and supplying the input signal to a plurality of memory cells arranged in one row. The signal propagating device includes a word line connected to transmit the input signal and having a plurality of line segments electrically coupled to the memory cells. A preceding one of the line segments is formed to have a larger average width than a succeeding one of the line segments.

摘要翻译： 提供了一种信号传播装置，用于在其输入端接收输入信号，并将输入信号提供给排列成一排的多个存储单元。 信号传播装置包括连接成传输输入信号并具有电耦合到存储器单元的多个线段的字线。 线段中的前一个被形成为具有比后面的一个线段更大的平均宽度。

公开(公告)号：US4616148A

公开(公告)日：1986-10-07

申请号：US792854

申请日：1985-10-30

申请人： Kiyofumi Ochii ,  Hiroshi Yasuda ,  Fujio Masuoka

发明人： Kiyofumi Ochii ,  Hiroshi Yasuda ,  Fujio Masuoka

IPC分类号： H03F3/345 ,  G11C7/06 ,  G11C11/419 ,  H03F3/34 ,  H03K3/356 ,  H03K5/24 ,  H03K3/023

CPC分类号： G11C7/065 ,  G11C7/062 ,  H03K3/356104

摘要： A sense amplifier in use for a memory device is made up of a pair of Schmitt trigger circuits. These Schmitt trigger circuits are cross coupled with each other so that each of the Schmitt trigger circuits operates in response to a predetermined high potential difference. The predetermined potential difference is high enough to operate each Schmitt trigger circuit according to the steeper slope of the two long slopes of a hysteresis loop of the Schmitt trigger circuit.

摘要翻译： 用于存储器件的读出放大器由一对施密特触发电路组成。 这些施密特触发电路彼此交叉耦合，使得施密特触发电路中的每一个响应于预定的高电位差工作。 预定的电位差足够高以根据施密特触发电路的磁滞回线的两个较大斜率的较陡斜率来操作每个施密特触发电路。

公开(公告)号：US08536002B2

公开(公告)日：2013-09-17

申请号：US13567552

申请日：2012-08-06

申请人： Hiroshi Yasuda ,  Berthold Staufer

发明人： Hiroshi Yasuda ,  Berthold Staufer

IPC分类号： H01L21/8238

CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L29/1004 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7833

摘要： A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.

摘要翻译： 通过使用非选择性外延工艺形成双极型晶体管的基极层，使得基极层在集电极有源区域上具有单一结晶区域和多晶硅层，形成包含双极晶体管和MOS晶体管的集成电路的工艺 区域，并且同时注入基极层的MOS栅极层和多晶区域，使得基极 - 集电极结延伸到小于场氧化物深度的三分之一的衬底中，并且垂直累积掺杂 基极层的多晶区域的密度在MOS栅极的垂直累积掺杂密度的80％至125％之间。 包含双极晶体管和通过所描述的工艺形成的MOS晶体管的集成电路。

公开(公告)号：US08450179B2

公开(公告)日：2013-05-28

申请号：US11670729

申请日：2007-02-02

申请人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Balster

发明人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Balster

IPC分类号： H01L21/331

CPC分类号： H01L29/7378 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0825 ,  H01L29/66242

摘要： A method for fabricating a semiconductor device having a first and second bipolar devices of the same dopant type includes: depositing a dielectric layer over a semiconductor layer, depositing a gate conductor layer over the dielectric layer, defining base regions of both bipolar devices, removing the gate conductor layer and dielectric layer in the base regions, depositing a base layer on the gate conductor layer and on the exposed semiconductor layer in the base regions, depositing an insulating layer over the base layer, forming a photoresist layer and defining emitter regions of both bipolar devices, removing the photoresist layer in the emitter regions thereby forming two emitter windows, masking the emitter window of the first bipolar device and exposing the base layer in the base region of the second bipolar device to an additional emitter implant through the associated emitter window.

摘要翻译： 一种用于制造具有相同掺杂剂类型的第一和第二双极器件的半导体器件的方法包括：在半导体层上沉积介电层，在电介质层上沉积栅极导体层，限定两个双极器件的基极区域， 栅极导体层和电介质层，在栅极导体层和基极区域的暴露的半导体层上沉积基底层，在基底层上沉积绝缘层，形成光致抗蚀剂层并限定两者的发射极区域 去除发射极区域中的光致抗蚀剂层，从而形成两个发射器窗口，掩蔽第一双极器件的发射极窗口，并将第二双极器件的基极区域中的基极层通过相关的发射极窗口暴露于另外的发射体注入 。

公开(公告)号：US08222619B2

公开(公告)日：2012-07-17

申请号：US12586717

申请日：2009-09-25

申请人： Akio Yamada ,  Hiroshi Yasuda ,  Mitsuhiro Nakano ,  Takashi Kiuchi

发明人： Akio Yamada ,  Hiroshi Yasuda ,  Mitsuhiro Nakano ,  Takashi Kiuchi

IPC分类号： A61N5/00 ,  G21G5/00

CPC分类号： B82Y40/00 ,  B82Y10/00 ,  H01J37/3045 ,  H01J37/3174 ,  H01J37/3177 ,  H01J2237/24507 ,  H01J2237/24521 ,  H01J2237/24535 ,  H01J2237/24542

摘要： A multi-column electron beam exposure apparatus includes: a plurality of column cells; a wafer stage including an electron-beam-property detecting unit for measuring an electron beam property; and a controller for measuring beam properties of electron beams used in all the column cells by using the electron-beam-property detecting unit, and for adjusting the electron beams of the respective column cells so that the properties of the electron beams used in the column cells may be approximately identical. The electron beam property may be any of a beam position, a beam intensity, and a beam shape of the electron beam to be emitted. The electron-beam-property detecting unit may be a chip for calibration with a reference mark formed thereon or a Faraday cup.

摘要翻译： 多列电子束曝光装置包括：多个柱单元; 包括用于测量电子束特性的电子束特性检测单元的晶片台; 以及用于通过使用电子束特性检测单元来测量在所有列单元中使用的电子束的光束特性的控制器，并且用于调节各列电池的电子束，使得在列中使用的电子束的性质 细胞可以大致相同。 电子束特性可以是要发射的电子束的光束位置，光束强度和光束形状中的任何一个。 电子束特性检测单元可以是用于在其上形成有参考标记的校准芯片或法拉第杯。

公开(公告)号：US20110226967A1

公开(公告)日：2011-09-22

申请号：US13068995

申请日：2011-05-25

申请人： Akio Yamada ,  Tomohiro Sakazaki ,  Hiroshi Yasuda

发明人： Akio Yamada ,  Tomohiro Sakazaki ,  Hiroshi Yasuda

IPC分类号： G21K5/00

CPC分类号： H01J37/3175 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/3174

摘要： An electron beam lithography apparatus includes a storage for storing data on a drawing pattern assigned a rank based on an accuracy required for a device pattern, a drawing pattern adjustment unit to generate data on divided drawing patterns based on the rank, a settlement wait time adjustment unit to determine a settlement wait time based on the rank, and a controller to draw the device pattern while irradiating an electron beam based on the data on the divided drawing patterns and the settlement wait time. The drawing pattern adjustment unit determines upper limits on the long-side length of a divided drawing pattern or on the area of the divided drawing pattern based on the rank, and divides the drawing pattern based on the upper limits.

摘要翻译： 一种电子束光刻设备，包括：存储器，用于根据设备图案所要求的准确度，对分配了等级的绘图图形进行数据存储;绘图模式调整单元，基于该等级生成分割图形的数据;结算等待时间调整 基于等级确定结算等待时间的单元，以及基于划分的绘图图案和结算等待时间的数据来照射电子束时绘制设备图案的控制器。 绘制图案调整单元基于等级来确定分割绘制图案的长边长度的上限或划分的绘制图案的区域的上限，并且基于上限划分绘图图案。

公开(公告)号：US20110057289A1

公开(公告)日：2011-03-10

申请号：US12718142

申请日：2010-03-05

申请人： Rick L. Wise ,  Hiroshi Yasuda

发明人： Rick L. Wise ,  Hiroshi Yasuda

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L29/36 ,  H01L21/02063 ,  H01L21/2254 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/7325

摘要： An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.

摘要翻译： 一种包含双极晶体管的集成电路，其包括具有高于1×1020原子/ cm3的峰值掺杂密度的发射极扩散区域，以及在基极层中小于40纳米深的发射极 - 基极结。 一种形成双极晶体管的工艺，其包括在基极层和发射极层之间形成发射极掺杂剂原子层，随后进行闪光或激光退火步骤，以将掺杂剂原子从发射极掺杂剂原子层扩散到基底层中。

公开(公告)号：US07847272B2

公开(公告)日：2010-12-07

申请号：US11235422

申请日：2005-09-26

申请人： Hiroshi Yasuda ,  Akio Yamada

发明人： Hiroshi Yasuda ,  Akio Yamada

IPC分类号： A61N5/00

CPC分类号： H01J37/3174 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/20 ,  H01J2237/31769

摘要： An electron beam exposure system is designed to correct a proximity effect. The electron beam exposure system includes: an electron beam generation unit for generating an electron beam; an electron beam exposure mask having opening portions that are arranged so that sizes of the opening portions change at a predetermined rate in order of arrangement; a mask deflection unit for deflecting the electron beam on the electron beam exposure mask; a substrate deflection unit for deflecting and projecting the electron beam onto a substrate; and a control unit for controlling deflection amounts in the mask deflection unit and the substrate deflection unit. The direction or directions of the change may be any one of a row direction and a column direction or may be the row and column directions.

摘要翻译： 电子束曝光系统设计用于校正邻近效应。 电子束曝光系统包括：用于产生电子束的电子束产生单元; 电子束曝光掩模，其具有开口部，其设置成使得开口部的尺寸按照布置的顺序以预定的速率变化; 用于使电子束在电子束曝光掩模上偏转的掩模偏转单元; 用于将电子束偏转和投影到衬底上的衬底偏转单元; 以及用于控制掩模偏转单元和基板偏转单元中的偏转量的控制单元。 改变的方向或方向可以是行方向和列方向中的任何一个，或者可以是行和列方向。