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公开(公告)号：US06891770B2
公开(公告)日：2005-05-10
申请号：US10920421
申请日：2004-08-18
IPC分类号： G11C11/403 , G11C8/18 , G11C11/406 , G11C11/408 , G11C7/00
CPC分类号： G11C8/18 , G11C11/406 , G11C11/408
摘要： Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.
摘要翻译： 响应于地址转换检测信号的前沿和后沿来控制用于控制存储器单元选择操作的内部正常行激活信号的激活/去激活。 当内部正常行激活信号被激活时，地址转换检测信号的产生被掩码电路掩蔽。 可以防止激活操作和正常行激活信号的失活操作之间的冲突，并且可以稳定地执行内部操作。 提供了一种具有与静态随机存取存储器兼容并且能够稳定地执行内部操作的接口的无刷新的动态半导体存储器件。
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公开(公告)号：US20060050587A1
公开(公告)日：2006-03-09
申请号：US11215994
申请日：2005-09-01
IPC分类号： G11C7/00
CPC分类号： G11C11/40603 , G11C8/18 , G11C11/406 , G11C11/40615
摘要： A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.
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公开(公告)号：US06956758B2
公开(公告)日：2005-10-18
申请号：US11049463
申请日：2005-02-03
IPC分类号： G11C11/403 , G11C11/406 , G11C8/00
CPC分类号： G11C11/40603 , G11C8/18 , G11C11/406 , G11C11/40615
摘要： A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.
摘要翻译： 复合栅极根据复合栅极的输出信号与地址转换检测信号之间的定时关系，检测内部阵列是处于选择状态还是内部行激活信号被激活。 当应用地址转换检测信号时，根据指示内部阵列是否处于选择状态的延迟恢复周期信号的产生定时和地址转换检测信号来允许下一行访问，内部行激活信号被去激活。 通过这样的配置，允许在内部状态确定地恢复到初始状态之后开始下一个操作。 当在恢复操作期间应用下一个地址转换检测信号，列恢复操作或刷新操作时，数据访问被正确地执行而不会导致数据破坏。
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公开(公告)号：US20060203607A1
公开(公告)日：2006-09-14
申请号：US11429291
申请日：2006-05-08
IPC分类号： G11C8/18
CPC分类号： G11C11/40603 , G11C8/18 , G11C11/406 , G11C11/40615
摘要： A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.
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公开(公告)号：US20050141337A1
公开(公告)日：2005-06-30
申请号：US11049463
申请日：2005-02-03
IPC分类号： G11C11/403 , G11C11/406 , G11C8/00
CPC分类号： G11C11/40603 , G11C8/18 , G11C11/406 , G11C11/40615
摘要： A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.
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公开(公告)号：US20050018529A1
公开(公告)日：2005-01-27
申请号：US10920421
申请日：2004-08-18
IPC分类号： G11C11/403 , G11C8/18 , G11C11/406 , G11C11/408 , G11C8/00
CPC分类号： G11C8/18 , G11C11/406 , G11C11/408
摘要： Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.
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公开(公告)号：US07145832B2
公开(公告)日：2006-12-05
申请号：US11429291
申请日：2006-05-08
IPC分类号： G11C8/00
CPC分类号： G11C11/40603 , G11C8/18 , G11C11/406 , G11C11/40615
摘要： A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.
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公开(公告)号：US07061828B2
公开(公告)日：2006-06-13
申请号：US11215994
申请日：2005-09-01
IPC分类号： G11C8/00
CPC分类号： G11C11/40603 , G11C8/18 , G11C11/406 , G11C11/40615
摘要： A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.
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公开(公告)号：US06859415B2
公开(公告)日：2005-02-22
申请号：US10352218
申请日：2003-01-28
IPC分类号： G11C11/403 , G11C11/406 , G11C11/00
CPC分类号： G11C11/40603 , G11C8/18 , G11C11/406 , G11C11/40615
摘要： A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.
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公开(公告)号：US06813211B2
公开(公告)日：2004-11-02
申请号：US10342289
申请日：2003-01-15
IPC分类号： G11C700
CPC分类号： G11C8/18 , G11C11/406 , G11C11/408
摘要： Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.
摘要翻译： 响应于地址转换检测信号的前沿和后沿来控制用于控制存储器单元选择操作的内部正常行激活信号的激活/去激活。 当内部正常行激活信号被激活时，地址转换检测信号的产生被掩码电路掩蔽。 可以防止激活操作和正常行激活信号的失活操作之间的冲突，并且可以稳定地执行内部操作。 提供了一种具有与静态随机存取存储器兼容并且能够稳定地执行内部操作的接口的无刷新的动态半导体存储器件。
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