公开(公告)号：US5777427A

公开(公告)日：1998-07-07

申请号：US539699

申请日：1995-10-05

申请人： Hiroyoshi Tanaka ,  Koichi Kotera ,  Masao Uchida

发明人： Hiroyoshi Tanaka ,  Koichi Kotera ,  Masao Uchida

IPC分类号： H01J1/304 ,  H01J9/02 ,  H01J1/02

CPC分类号： B82Y10/00 ,  H01J1/3042 ,  H01J9/025 ,  H01J2201/30403 ,  H01J2201/30457 ,  H01J2329/00

摘要： An electron emission cathode includes: an n-type semiconductor film including diamond particles partially projecting from a surface of the n-type semiconductor film; and an anode opposing the n-type semiconductor film with a vacuum interposed therebetween. Electrons are emitted by applying a voltage between the anode and the n-type semiconductor film.

摘要翻译： 电子发射阴极包括：n型半导体膜，包括从n型半导体膜的表面部分地突出的金刚石颗粒; 以及与之间的真空相对的n型半导体膜的阳极。 通过在阳极和n型半导体膜之间施加电压来发射电子。

公开(公告)号：US5984752A

公开(公告)日：1999-11-16

申请号：US47131

申请日：1998-03-24

申请人： Hiroyoshi Tanaka ,  Koichi Kotera ,  Masao Uchida

发明人： Hiroyoshi Tanaka ,  Koichi Kotera ,  Masao Uchida

IPC分类号： H01J1/304 ,  H01J9/02

CPC分类号： B82Y10/00 ,  H01J1/3042 ,  H01J9/025 ,  H01J2201/30403 ,  H01J2201/30457 ,  H01J2329/00

摘要： An electron emission cathode includes: an n-type semiconductor film including diamond particles partially projecting from a surface of the n-type semiconductor film; and an anode opposing the n-type semiconductor film with a vacuum interposed therebetween. Electrons are emitted by applying a voltage between the anode and the n-type semiconductor film.

摘要翻译： 电子发射阴极包括：n型半导体膜，包括从n型半导体膜的表面部分地突出的金刚石颗粒; 以及与之间的真空相对的n型半导体膜的阳极。 通过在阳极和n型半导体膜之间施加电压来发射电子。

公开(公告)号：US08933463B2

公开(公告)日：2015-01-13

申请号：US13780876

申请日：2013-02-28

申请人： Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Koichi Hashimoto ,  Shun Kazama

发明人： Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Koichi Hashimoto ,  Shun Kazama

IPC分类号： H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H03K17/14 ,  H01L29/45

CPC分类号： H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7805 ,  H01L29/7827 ,  H01L29/7828 ,  H03K17/145

摘要： A semiconductor element including an MISFET exhibits diode characteristics in a reverse direction through an epitaxial channel layer. The semiconductor element includes: a silicon carbide semiconductor substrate of a first conductivity type, semiconductor layer of the first conductivity type, body region of a second conductivity type, source region of the first conductivity type, epitaxial channel layer in contact with the body region, source electrode, gate insulating film, gate electrode and drain electrode. If the voltage applied to the gate electrode is smaller than a threshold voltage, the semiconductor element functions as a diode wherein current flows from the source electrode to the drain electrode through the epitaxial channel layer. The absolute value of the turn-on voltage of this diode is smaller than the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.

摘要翻译： 包括MISFET的半导体元件通过外延沟道层在相反方向上表现出二极管特性。 半导体元件包括：第一导电类型的碳化硅半导体衬底，第一导电类型的半导体层，第二导电类型的主体区域，第一导电类型的源极区域，与身体区域接触的外延沟道层， 源电极，栅极绝缘膜，栅电极和漏电极。 如果施加到栅电极的电压小于阈值电压，则半导体元件用作二极管，其中电流从源电极通过外延沟道层流到漏电极。 该二极管的导通电压的绝对值小于由体区和第一碳化硅半导体层形成的体二极管的导通电压。

公开(公告)号：US08283973B2

公开(公告)日：2012-10-09

申请号：US13389555

申请日：2010-08-09

申请人： Koichi Hashimoto ,  Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Shun Kazama

发明人： Koichi Hashimoto ,  Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Shun Kazama

IPC分类号： G05F3/02

CPC分类号： H01L29/7828 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7838 ,  H02M7/5387 ,  Y02B70/1483

摘要： A semiconductor element 100 including an MISFET according to the present invention is characterized by having diode characteristics in a reverse direction through an epitaxial channel layer 50. The semiconductor element 100 includes a semiconductor layer 20 of a first conductivity type, a body region 30 of a second conductivity type, source and drain regions 40 and 75 of the first conductivity type, an epitaxial channel layer 50 in contact with the body region, source and drain electrodes 45 and 70, a gate insulating film 60, and a gate electrode 65. If the voltage applied to the gate electrode of the MISFET is smaller than a threshold voltage, the semiconductor element 100 functions as a diode in which current flows from the source electrode 45 to the drain electrode 70 through the epitaxial channel layer 50. The absolute value of the turn-on voltage of this diode is smaller than that of the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.

摘要翻译： 包括根据本发明的MISFET的半导体元件100的特征在于通过外延沟道层50在相反方向上具有二极管特性。半导体元件100包括第一导电类型的半导体层20，第一导电类型的体区30 第二导电类型，第一导电类型的源极和漏极区域40和75，与主体区域接触的外延沟道层50，源极和漏极电极45和70，栅极绝缘膜60和栅电极65.如果 施加到MISFET的栅电极的电压小于阈值电压，半导体元件100用作二极管，其中电流通过外延沟道层50从源电极45流到漏极70。绝对值 该二极管的导通电压小于由体区和第一硅碳化物形成的体二极管的导通电压的导通电压 e半导体层。

公开(公告)号：US20120057386A1

公开(公告)日：2012-03-08

申请号：US13266271

申请日：2010-04-28

申请人： Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Koichi Hashimoto ,  Shun Kazama

发明人： Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Koichi Hashimoto ,  Shun Kazama

IPC分类号： H02M7/537 ,  H01L29/24

CPC分类号： H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7805 ,  H01L29/7827 ,  H01L29/7828 ,  H03K17/145

摘要： A semiconductor element 100 including an MISFET according to the present invention is characterized by having diode characteristics in a reverse direction through an epitaxial channel layer 50. The semiconductor element 100 includes a silicon carbide semiconductor substrate 10 of a first conductivity type, a semiconductor layer 20 of the first conductivity type, a body region 30 of a second conductivity type, a source region 40 of the first conductivity type, an epitaxial channel layer 50 in contact with the body region, a source electrode 45, a gate insulating film 60, a gate electrode 65 and a drain electrode 70. If the voltage applied to the gate electrode of the MISFET is smaller than a threshold voltage, the semiconductor element 100 functions as a diode in which current flows from the source electrode 45 to the drain electrode 70 through the epitaxial channel layer 50. The absolute value of the turn-on voltage of this diode is smaller than that of the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.

摘要翻译： 包括根据本发明的MISFET的半导体元件100的特征在于通过外延沟道层50在相反方向上具有二极管特性。半导体元件100包括第一导电类型的碳化硅半导体衬底10，半导体层20 第一导电类型的体区30，第一导电类型的源极区40，与体区接触的外延沟道层50，源电极45，栅极绝缘膜60， 栅电极65和漏电极70.如果施加到MISFET的栅电极的电压小于阈值电压，则半导体元件100用作二极管，其中电流从源电极45流到漏电极70通过 外延沟道层50.该二极管的导通电压的绝对值小于体二的导通电压的绝对值 由所述体区和所述第一碳化硅半导体层形成。

公开(公告)号：US20110207275A1

公开(公告)日：2011-08-25

申请号：US13126112

申请日：2010-07-28

申请人： Koutarou Tanaka ,  Masahiko Niwayama ,  Masao Uchida

发明人： Koutarou Tanaka ,  Masahiko Niwayama ,  Masao Uchida

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068

摘要： A method of producing a semiconductor device according to the present invention includes: a step of implanting an impurity into a semiconductor layer 2 by using a first implantation mask layer 30, thereby forming a body region 6; a step of implanting an impurity by using the first implantation mask layer 30 and a second implantation mask layer 31, thereby forming a contact region 7 within the body region 6; a step of forming a third implantation mask layer 32, and thereafter selectively removing the second implantation mask layer 31; a step of forming a side wall 34 on a side face of the first implantation mask layer 30; and a step of implanting an impurity to form a source region 8 within the body region 6.

摘要翻译： 根据本发明的制造半导体器件的方法包括：通过使用第一注入掩模层30将杂质注入半导体层2，从而形成体区6的步骤; 通过使用第一注入掩模层30和第二注入掩模层31注入杂质的步骤，从而在体区6内形成接触区7; 形成第三注入掩模层32的步骤，然后选择性地除去第二注入掩模层31; 在第一注入掩模层30的侧面上形成侧壁34的步骤; 以及植入杂质以在体区6内形成源区8的步骤。

公开(公告)号：US07846828B2

公开(公告)日：2010-12-07

申请号：US12338395

申请日：2008-12-18

申请人： Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Masahiro Hagio ,  Kazuyuki Sawada

发明人： Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Masahiro Hagio ,  Kazuyuki Sawada

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L29/7828 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/30625 ,  H01L29/1029 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7838 ,  H01L29/812

摘要： Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

摘要翻译： 进行离子注入以在SiC衬底上的高电阻SiC层的部分中形成p阱区域和源极区域，并且在衬底上沉积碳膜。 通过沉积在基板上的碳膜，进行用于激活注入的掺杂离子的退火，然后除去碳膜。 因此，获得了退火几乎没有表面粗糙度的光滑表面。 此外，如果沟道层外延生长，则沟道层的表面粗糙度小于下层的表面粗糙度。 由于提供了具有平滑表面的沟道层，所以可以获得具有高电流驱动能力的MISFET。

公开(公告)号：US20100207125A1

公开(公告)日：2010-08-19

申请号：US12676415

申请日：2008-10-24

申请人： Masao Uchida ,  Kazuya Utsunomiya ,  Masashi Hayashi

发明人： Masao Uchida ,  Kazuya Utsunomiya ,  Masashi Hayashi

IPC分类号： H01L29/24 ,  H01L21/04

CPC分类号： H01L29/66068 ,  H01L21/0485 ,  H01L29/45 ,  H01L29/6606 ,  H01L29/7828 ,  H01L29/872

摘要： A semiconductor device according to the present invention includes: a silicon carbide substrate (11) that has a principal surface and a back surface; a semiconductor layer (12), which has been formed on the principal surface of the silicon carbide substrate; and a back surface ohmic electrode layer (1d), which has been formed on the back surface of the silicon carbide substrate. The back surface ohmic electrode layer (1d) includes: a reaction layer (1da), which is located closer to the back surface of the silicon carbide substrate and which includes titanium, silicon and carbon; and a titanium nitride layer (1db), which is located more distant from the back surface of the silicon carbide substrate.

摘要翻译： 根据本发明的半导体器件包括：具有主表面和后表面的碳化硅衬底（11）; 半导体层（12），其形成在所述碳化硅衬底的主表面上; 以及形成在碳化硅基板的背面上的背面欧姆电极层（1d）。 背面欧姆电极层（1d）包括：反应层（1da），其位于更靠近碳化硅基板的背面，并且包括钛，硅和碳; 和位于比碳化硅衬底的背面更远的氮化钛层（1db）。

公开(公告)号：US20090101918A1

公开(公告)日：2009-04-23

申请号：US12300352

申请日：2007-05-17

申请人： Masao Uchida ,  Koichi Hashimoto ,  Masashi Hayashi

发明人： Masao Uchida ,  Koichi Hashimoto ,  Masashi Hayashi

IPC分类号： H01L29/12 ,  H01L21/04

CPC分类号： H01L29/7802 ,  H01L21/046 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/66068 ,  H01L29/7828

摘要： A semiconductor device includes: a semiconductor layer 10; a semiconductor region 15s of a first conductivity type defined on the surface 10s of the semiconductor layer; a semiconductor region 14s of a second conductivity type defined on the surface 10s of the semiconductor layer to surround the semiconductor region 15s; and a conductor 19 with a conductive surface 19s to contact with the semiconductor regions 15s and 14s. The semiconductor layer 10 includes silicon carbide. At least one of the semiconductor region 15s and the conductive surface 19s is not circular. The semiconductor region 15s and the conductive surface 19s are shaped such that as the degree of misalignment between the conductive surface 19s and the semiconductor region 15s increases from zero through one-third of the width of the conductive surface 19s, a portion of the profile of the conductive surface 19s that crosses the semiconductor region 15s has smoothly changing lengths.

摘要翻译： 半导体器件包括：半导体层10; 限定在半导体层的表面10s上的第一导电类型的半导体区域15s; 限定在半导体层的表面10s上以包围半导体区域15s的第二导电类型的半导体区域14s; 以及具有导电表面19s以与半导体区域15s和14s接触的导体19。 半导体层10包括碳化硅。 半导体区域15s和导电表面19s中的至少一个不是圆形的。 半导体区域15s和导电表面19s被成形为使得当导电表面19s和半导体区域15s之间的未对准程度从零增加到导电表面19s的宽度的三分之一时，轮廓的一部分 穿过半导体区域15s的导电表面19s具有平滑变化的长度。

公开(公告)号：US07462540B2

公开(公告)日：2008-12-09

申请号：US10553845

申请日：2005-01-28

申请人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Kenya Yamashita ,  Masao Uchida ,  Osamu Kusumoto ,  Ryoko Miyanaga

发明人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Kenya Yamashita ,  Masao Uchida ,  Osamu Kusumoto ,  Ryoko Miyanaga

IPC分类号： H01L21/00

CPC分类号： H01L21/046

摘要： A method for fabricating a semiconductor device includes the steps of implanting ions into a silicon carbide thin film (2) formed on a silicon carbide substrate (1), heating the silicon carbide substrate in a reduced pressure atmosphere to form a carbon layer (5) on the surface of the silicon carbide substrate, and performing activation annealing with respect to the silicon carbide substrate in an atmosphere under a pressure higher than in the step of forming the carbon layer (5) and at a temperature higher than in the step of forming the carbon layer (5).

摘要翻译： 一种制造半导体器件的方法包括以下步骤：将离子注入形成在碳化硅衬底（1）上的碳化硅薄膜（2）中，在减压气氛中加热碳化硅衬底以形成碳层（5） 在碳化硅衬底的表面上，并且在比形成碳层（5）的步骤高的压力的气氛中，并且在高于形成步骤的温度的气氛中，相对于碳化硅衬底进行激活退火 碳层（5）。