Receiver circuit
    2.
    发明授权
    Receiver circuit 有权
    接收电路

    公开(公告)号:US08483263B2

    公开(公告)日:2013-07-09

    申请号:US12926834

    申请日:2010-12-13

    申请人: Yasushi Aoki

    发明人: Yasushi Aoki

    IPC分类号: H04L27/00

    摘要: A receiver circuit includes an equalizer circuit that adjusts reception intensity of an input signal based on an intensity adjustment value to generate a correction input signal; a first holding unit that holds a plurality of data items sampled based on a sampling clock for sampling values of the data items transmitted by the correction input signal in a receiving order; a second holding unit that holds a plurality of values of the correction input signal sampled based on a complementary sampling clock for sampling a boundary value of the data items in a receiving order; and an equalizer control circuit that judges the strength of reception intensity of the correction input signal based on a plurality of output signals of the first holding unit and a plurality of output signals of the second holding unit to update the intensity adjustment value based on the judgment result.

    摘要翻译: 接收机电路包括均衡器电路,其基于强度调整值调整输入信号的接收强度以产生校正输入信号; 第一保持单元,其保持基于采样时钟采样的多个数据项,用于以接收顺序对由校正输入信号发送的数据项进行采样; 第二保持单元,其基于用于以接收次序对数据项的边界值进行采样的补充采样时钟,保持被采样的校正输入信号的多个值; 以及均衡器控制电路,其基于所述第一保持单元的多个输出信号和所述第二保持单元的多个输出信号来判定所述校正输入信号的接收强度的强度,以基于所述判断来更新所述强度调整值 结果。

    Infra-Red Light Emitting Phosphor
    3.
    发明申请
    Infra-Red Light Emitting Phosphor 有权
    红外线发光荧光粉

    公开(公告)号:US20090267027A1

    公开(公告)日:2009-10-29

    申请号:US11817967

    申请日:2006-03-27

    IPC分类号: C09K11/78

    摘要: It is an object of the present invention to provide an infra-red light emitting phosphor having an excellent chemical stability and desirable light emitting properties. The infra-red light emitting phosphor is represented by a chemical formula: (A1-x-yNdxYby)VO4, wherein A represents at least one element selected from yttrium (Y), gadolinium (Gd), lutetium (Lu) and lanthanum (La); x and y respectively satisfy the requirements: 0.01≦x≦0.3 and 0.01≦y≦0.4, provided that (x+y)≦0.5 and 0.2≦(y/x)≦6. This vanadate phosphor having the constitution described above can act as an infra-red light emitting phosphor having an excellent chemical stability and desirable light emitting properties.

    摘要翻译: 本发明的目的是提供一种具有优异的化学稳定性和理想的发光特性的红外发光荧光体。 红外发光荧光体由化学式(A1-x-yNdxYby)VO4表示,其中A表示选自钇(Y),钆(Gd),镥(Lu)和镧(La)中的至少一种元素 ); x和y分别满足要求:0.01 <= x <= 0.3和0.01 <= y <= 0.4,条件是(x + y)<= 0.5和0.2 <=(y / x)<= 6。 具有上述结构的钒酸盐荧光体可以用作具有优异的化学稳定性和期望的发光性质的红外发光荧光体。

    Hydraulic brake device
    4.
    发明授权
    Hydraulic brake device 有权
    液压制动装置

    公开(公告)号:US07517027B2

    公开(公告)日:2009-04-14

    申请号:US11333634

    申请日:2006-01-17

    IPC分类号: B60T8/44 B60T8/88

    CPC分类号: B60T13/147 B60T13/145

    摘要: A normally closed secondary solenoid opening/closing valve 36 is provided along a secondary branched fluid pipe 35 establishing a communication between an accumulator 11 and a reservoir 8 through a fluid pressure input side to a fluid pressure output side of a regulator valve 3, and in the event that a fluid pressure supplied to the regulator valve 3 decreases down to or lower than a predetermined range due to something abnormal occurring in the accumulator 11, the state of the secondary solenoid opening/closing valve 36 is changed over from a closed state to an opened state, whereby a residual pressure in the accumulator 11 and a residual pressure in the output fluid pressure chamber 15 can be released through the reservoir 8 which is in communication therewith through an output fluid pipe 31 and the secondary branched fluid pipe 35 along which the secondary opening/closing valve 36 is provided.

    摘要翻译: 沿着次级分支流体管35设置常闭的次级电磁开闭阀36,其通过流体压力输入侧到调节阀3的流体压力输出侧,建立蓄能器11和储存器8之间的连通,并且 由于蓄能器11中发生异常而导致供给到调节阀3的流体压力下降到规定范围以下的事件,二次螺线管开闭阀36的状态从关闭状态切换到 打开状态,由此可以通过与其连通的储存器8通过输出流体管31和辅助分支流体管35将累积器11中的残余压力和输出流体压力室15中的残留压力释放 设置有二次开闭阀36。

    Level converter and semiconductor device
    5.
    发明申请
    Level converter and semiconductor device 失效
    电平转换器和半导体器件

    公开(公告)号:US20080042725A1

    公开(公告)日:2008-02-21

    申请号:US11878743

    申请日:2007-07-26

    申请人: Yasushi Aoki

    发明人: Yasushi Aoki

    IPC分类号: H03L5/00

    CPC分类号: H03K19/018528

    摘要: A level converter includes a first to fourth transistors formed of a semiconductor having a same conductivity type. The first transistor is connected between a first power supply and a second output terminal, the second transistor is connected between a second power supply and a first output terminal, the third transistor is connected between the first power supply and the first output terminal, the fourth transistor is connected between the second power supply and the second output terminal, the first and the second transistors are input with one of first differential signals and the third and the fourth transistors are input with another of the first differential signals.

    摘要翻译: 电平转换器包括由具有相同导电类型的半导体形成的第一至第四晶体管。 第一晶体管连接在第一电源和第二输出端之间,第二晶体管连接在第二电源和第一输出端之间,第三晶体管连接在第一电源与第一输出端之间, 晶体管连接在第二电源和第二输出端之间,第一和第二晶体管以第一差分信号中的一个输入,第三和第四晶体管与另一个第一差分信号一起输入。

    Pre-emphasis circuit
    6.
    发明申请
    Pre-emphasis circuit 有权
    预加重电路

    公开(公告)号:US20070024476A1

    公开(公告)日:2007-02-01

    申请号:US11493602

    申请日:2006-07-27

    IPC分类号: H03M9/00

    CPC分类号: H03M9/00

    摘要: Disclosed is a pre-emphasis circuit including a first parallel-to-serial converter, a second parallel-to-serial converter, a mixing circuit and a clock generating circuit. The first parallel-to-serial converter converts parallel data into first serial data, and the second parallel-to-serial converter converts the parallel data into second serial data. The mixing circuit receives the first serial data from the first parallel-to-serial converter and the second serial data from the second parallel-to-serial converter to output a signal emphasizing a change point of the first serial data. The clock generating circuit outputs a first set of clocks made up of clocks having mutually different phases and a second set of clocks made up of clocks having mutually different phases to the first and second parallel-to-serial converters, respectively. The first phase clock of the second set of clocks corresponds to the second phase clock of the first set of clocks.

    摘要翻译: 公开了一种包括第一并行转换器,第二并行到串行转换器,混合电路和时钟发生电路的预加重电路。 第一个并行到串行转换器将并行数据转换为第一个串行数据,第二个并行到串行转换器将并行数据转换成第二个串行数据。 混合电路从第一并行转换器接收第一串行数据和来自第二并行 - 串行转换器的第二串行数据,以输出强调第一串行数据的变化点的信号。 时钟发生电路分别输出由具有相互不同相位的时钟构成的第一组时钟和由具有相互不同相位的时钟组成的第二组时钟,分别与第一和第二并行 - 串行转换器。 第二组时钟的第一相位时钟对应于第一组时钟的第二相位时钟。

    Fluid pressure booster
    7.
    发明申请

    公开(公告)号:US20060230757A1

    公开(公告)日:2006-10-19

    申请号:US11389501

    申请日:2006-03-27

    IPC分类号: B60T13/00

    CPC分类号: B60T11/224

    摘要: A fluid pressure booster includes: a control piston in which brake operation input acts in an advancing direction, and reaction based on fluid pressure of a booster fluid pressure generation chamber that generates fluid pressure for actuating a master piston acts in a retracting direction; a pressure increasing valve provided between the booster fluid pressure generation chamber and a fluid pressure generation source so as to open at the time of advance of the control piston and close at the time of retraction of the control piston; and a pressure reducing valve provided between a release chamber and the booster fluid pressure generation chamber so as to close at the time of the advance of the control piston and open at the time of the retraction of the control piston. The pressure increasing valve includes first valve means and second valve means that sequentially open according to an increase in the brake operation input, and a seal diameter of the second valve means is larger than that of the first valve means. Thus, it is possible to enhance initial response of the pressure increasing valve, and also enhance response of the pressure increasing valve when a brake operation member is strongly operated.

    Brake control device
    8.
    发明申请

    公开(公告)号:US20060197373A1

    公开(公告)日:2006-09-07

    申请号:US11360319

    申请日:2006-02-23

    IPC分类号: B60T13/18

    CPC分类号: B60T13/145 B60T8/441 B60T8/88

    摘要: A brake control device is provided, which is capable of providing a precise diagnosis on a trouble on a hydraulic pressure valve etc., so as to provide an appropriate output hydraulic pressure corresponding to a stroke amount of a brake pedal. In this device, an electromagnetic valve is provided on a hydraulic pressure passage allowing an auxiliary hydraulic pressure chamber to communicate with an accumulator, and is controlled to open when such a trouble occurs that output hydraulic pressure from the hydraulic pressure valve becomes lower than a predetermined range; and an electromagnetic valve is also provided on a hydraulic pressure passage allowing the auxiliary hydraulic pressure chamber to communicate with a reservoir, and is controlled to open when such a trouble occurs that the output hydraulic pressure from the hydraulic pressure valve becomes insufficiently reduced.

    Differential output circuit for improving bandwidth
    9.
    发明授权
    Differential output circuit for improving bandwidth 有权
    差分输出电路,用于提高带宽

    公开(公告)号:US06967504B2

    公开(公告)日:2005-11-22

    申请号:US10671678

    申请日:2003-09-29

    申请人: Yasushi Aoki

    发明人: Yasushi Aoki

    CPC分类号: H03K3/356113 H03K3/356165

    摘要: A differential output circuit includes first and second inputs, first and second outputs, a resistor element connected between the outputs, first and second N-channel MISFETs, and first and second P-channel MISFETs. The inputs respectively receive first and second complementary input signals. The first N-channel MISFET has a source connected to the first input, a gate receiving a power supply potential, and a drain connected to the first output. The second N-channel MISFET has a source connected to the second input, a gate receiving the power supply potential, and a drain connected to the second output. The first P-channel MISFET has a source receiving the power supply potential, a gate connected to the second input, and a drain connected to the first output. The second P-channel MISFET has a source receiving the power supply potential, a gate connected to the first input, and a drain connected to the second output.

    摘要翻译: 差分输出电路包括第一和第二输入,第一和第二输出,连接在输出端,第一和第二N沟道MISFET之间的电阻元件以及第一和第二P沟道MISFET。 输入分别接收第一和第二互补输入信号。 第一N沟道MISFET具有连接到第一输入端的源极,接收电源电位的栅极和连接到第一输出端的漏极。 第二N沟道MISFET具有连接到第二输入端的源极,接收电源电位的栅极和连接到第二输出端的漏极。 第一P沟道MISFET具有接收电源电位的源极,连接到第二输入端的栅极和连接到第一输出端的漏极。 第二P沟道MISFET具有接收电源电位的源极,连接到第一输入端的栅极和连接到第二输出端的漏极。

    Clock data recovery circuit with improved jitter transfer characteristics and jitter tolerance
    10.
    发明授权
    Clock data recovery circuit with improved jitter transfer characteristics and jitter tolerance 有权
    时钟数据恢复电路具有改善的抖动传输特性和抖动容限

    公开(公告)号:US06903587B2

    公开(公告)日:2005-06-07

    申请号:US10614830

    申请日:2003-07-09

    摘要: A clock extracting part has a first phase comparator circuit, a first up/down counter, a weighting circuit, a charge pump and a low-pass filter forming a voltage value determining part, and a voltage controlled oscillator circuit. A retiming clock generating part has a second up/down counter and a phase switching circuit. Furthermore, a phase adjusting part has a first counter, a second counter, a second phase comparator circuit and a third up/down counter forming a phase adjusting part. A clock data recovery circuit is formed by said clock extracting part, the retiming clock generating part, the phase adjusting part, and a first-in first-out memory part. Thereby, a clock data recovery circuit is obtained, in which jitter transfer characteristics and jitter tolerance satisfy the standards of both the SONET and SDH.

    摘要翻译: 时钟提取部分具有第一相位比较器电路,第一上/下计数器,加权电路,电荷泵和形成电压值确定部分的低通滤波器以及压控振荡器电路。 重新定时钟产生部件具有第二上/下计数器和相位切换电路。 此外,相位调整部具有形成相位调整部的第一计数器,第二计数器,第二相位比较电路和第三上/下计数器。 时钟数据恢复电路由所述时钟提取部分,重新​​定时钟产生部分,相位调整部分和先进先出存储器部分构成。 由此,获得抖动传递特性和抖动容限满足SONET和SDH两者的标准的时钟数据恢复电路。