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公开(公告)号：US5353404A
公开(公告)日：1994-10-04
申请号：US468271
申请日：1990-01-22
CPC分类号： G06T1/60
摘要： Frames of digital data each representing a single picture of a video motion picture display are handled in a computer system with an extended memory operating in parallel with a computer system instruction processor and main memory to bypass the computer system input/output processor for continuously outputting the video information on a real time basis. The outputted data may be recorded continuously at a constant data rate for an entire motion picture worth of information or actually displayed on the video display on a real time basis. The extended storage has a memory larger than the main memory, where all of the frame data is stored and read out in high speed bursts to a buffer that continuously reads the data out of the buffer for outputting. At least a start command and a starting address in the extended memory are contained within the main memory to be read out and decoded by the instruction processor and computer system memory storage control, for transfer to the extended memory, where they are used to start the program, which includes extended memory control words stored in the main memory, which control words are decoded and executed in the extended memory in parallel with the computer system instruction processor. Addresses of succeeding frames are generated and decoded and used for fetching entirely within the extended memory, for memory areas according to indirect addressing. The extended memory has external data transfer and internal data transfer registers that hold command words for respective transferring programs that may be operated in parallel, with conflict between external transfer and internal transfer being decided in favor of external transfer to assure continuous data outputting.
摘要翻译： 在计算机系统中处理每个表示视频运动图像显示的单个图像的数字数据帧，其中扩展存储器与计算机系统指令处理器和主存储器并行操作，以绕过计算机系统输入/输出处理器，以连续输出 视频信息实时基础。 输出的数据可以以恒定的数据速率连续地记录整个运动画面的信息，或实时显示在视频显示器上。 扩展存储器具有大于主存储器的存储器，其中所有帧数据以高速脉冲串存储和读出到缓冲器，该缓冲器从缓冲器中连续读取数据以供输出。 扩展存储器中的起始命令和起始地址至少包含在主存储器内，以由指令处理器和计算机系统存储器存储控制进行读出和解码，以传送到扩展存储器，在那里它们被用于启动 程序，其包括存储在主存储器中的扩展存储器控制字，该控制字与计算机系统指令处理器并行地在扩展存储器中被解码和执行。 生成并解码后续帧的地址，并将其用于根据间接寻址完全在扩展存储器内获取存储区域。 扩展存储器具有外部数据传输和内部数据传输寄存器，其保存可以并行操作的相应传送程序的命令字，外部传输和内部传输之间的冲突被决定有利于外部传输以确保连续的数据输出。
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公开(公告)号：US4617625A
公开(公告)日：1986-10-14
申请号：US453094
申请日：1982-12-27
CPC分类号： G06F15/8084 , G06F9/3836 , G06F9/3838 , G06F9/3859 , G06F9/3867 , G06F9/4436
摘要： A data processor has a plurality of vector registers capable of reading and writing in parallel; a plurality of ALU's; a plurality of sending circuits, one for each of said vector registers, each for updating a read address for the corresponding vector register requested by a succeeding instruction within such a limit that said read address does not pass a write address for said corresponding vector register requested by a preceding instruction and sending out a read data together with a data valid signal for each updating; circuits for sending the data and the data valid signals from said plurality of sending circuits to the ALU's requested by the corresponding instructions; and circuits, one for each of said ALU's, each for controlling the corresponding ALU such that when the data valid signals have been received from all of the vector registers necessary to execute the instruction which uses the corresponding ALU, the corresponding ALU operates on the data supplied with said data valid signals and sends out a data valid signal.
摘要翻译： 数据处理器具有能够并行读写的多个向量寄存器; 多个ALU; 多个发送电路，每个所述向量寄存器一个，用于在所述读取地址不通过所请求的所述对应向量寄存器的写入地址的限制内更新由后续指令请求的对应向量寄存器的读取地址 通过前一条指令发送读取的数据以及每次更新的数据有效信号; 用于将数据和数据有效信号从所述多个发送电路发送到由相应指令请求的ALU的电路; 以及用于每个所述ALU的电路，每个用于控制对应的ALU，使得当已经从执行使用相应的ALU的指令所需的所有向量寄存器接收到数据有效信号时，相应的ALU对数据进行操作 提供所述数据有效信号并发出数据有效信号。
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公开(公告)号：US06533860B1
公开(公告)日：2003-03-18
申请号：US09763354
申请日：2001-02-21
IPC分类号： C09B6722
CPC分类号： H05K3/287 , C09B67/0033 , H05K1/0269 , H05K2203/161
摘要： A method for preparing a green pigment composition in which a mixture of a halogen-free organic blue pigment material and a halogen-free organic yellow pigment material are subjected to an atomizing process. The atomizing process is desirably (1) a co-kneading process conducted in the presence of a grinding material, or (2) a process that comprises dissolving the above-mentioned blue pigment material and yellow pigment material in a strong acid to obtain a solution, and injecting this solution into water to obtain a re-deposited substance. The method prevents the “fogging” problem, and provides high quality green shade having simultaneously sufficient light resistance and heat resistance. The resulting organic pigment composition is excellent also in plastics coloring use requiring a heating process at higher temperature, and has high safety/sanitation property, and causes no environmental problem.
摘要翻译： 一种制备绿色颜料组合物的方法，其中无卤有机蓝颜料和无卤有机黄颜料的混合物进行雾化处理。 雾化方法优选为（1）在研磨材料存在下进行的共捏合工序，或者（2）将上述蓝色颜料和黄色颜料在上述溶液中溶解，得到溶液 ，并将该溶液注入水中以获得再沉积物质。 该方法防止“雾化”问题，并提供具有同时足够的耐光性和耐热性的高质量绿色阴影。 所得到的有机颜料组合物在用于需要在较高温度下进行加热处理的塑料着色用途中也是优异的，并且具有高的安全/卫生性能，并且不会引起环境问题。
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4.发明授权Address conversion for a multiprocessor system having scalar and vector processors 失效具有标量和向量处理器的多处理器系统的地址转换
公开(公告)号：US4769770A
公开(公告)日：1988-09-06
申请号：US807684
申请日：1985-12-11
CPC分类号： G06F12/0284
摘要： An information processing apparatus having an address translation system includes a plurality of processors in each of which an addressing is carried out by translating a logical address into a real address in the virtual storage system for data processing. The plurality of processors include a scalar processor for translating a logical address into a real address by using an address translation table; and a vector processor for determining if the logical address to be relocated lies within a predetermined address range, for address-relocating the logical address to the real address based on a relocation table when the logical address lies within the predetermined address range, and using the logical address as a real address when the logical address lies outside of the predetermined address range. The predetermined address range and the content of the relocation table are set by the scalar processor which supervises the program storage area.
摘要翻译： 具有地址转换系统的信息处理装置包括多个处理器，每个处理器通过将逻辑地址转换为虚拟存储系统中的实际地址进行数据处理来执行寻址，用于数据处理。 多个处理器包括标量处理器，用于通过使用地址转换表将逻辑地址转换成真实地址; 以及矢量处理器，用于确定要重定位的逻辑地址是否在预定地址范围内，用于当逻辑地址位于预定地址范围内时，基于重定位表将逻辑地址重定位到实地址，并且使用 逻辑地址作为逻辑地址位于预定地址范围之外的实地址。 预定地址范围和重定位表的内容由监控程序存储区域的标量处理器设置。
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5.发明申请Optical sheet body and its producing method, optical card and composite memory 审中-公开光学片体及其制作方法，光卡和复合记忆体公开(公告)号：US20070172187A1
公开(公告)日：2007-07-26
申请号：US10581798
申请日：2003-12-03
IPC分类号： G02B6/10
CPC分类号： G06K19/06046 , G02B6/122 , G02B2006/1219 , G06K19/06009
摘要： An optical card (1) comprising a surface protection sheet (4) laid on the surface (2a) of a core sheet (2) through a surface side adhesive layer (3) functioning as a surface-side clad layer, and a back surface protection sheet (6) laid on the back surface (2b) through a back surface side adhesive layer (5) functioning as a back surface-side clad layer, wherein a large number of V-grooves (7) are made, at a constant interval, in the surface (2a) of the core sheet (2) and the opposite ends (7a, 7b) of each V-groove are exposed to the end faces (2c,2d) of the sheet. Sectional parts (8(2), 8(4), . . . ) of the core sheet (2) formed between respective grooves (7) function as optical waveguides and remaining sectional parts (8(1), 8(3), . . . ) each provided with a V-groove (light shielding groove) (9) extending across adjacent V-grooves (7), function as non-optical waveguides. An inexpensive and highly durable optical card (1) having optical waveguides and non-optical waveguides formed with high accuracy can thereby be provided without using an optical fiber.
摘要翻译： 1.一种光卡（1），其特征在于，包括通过作为表面侧覆层的表面侧粘接层（3）而放置在芯片（2）的表面（2a）上的表面保护片（4） 表面保护片（6）通过用作后表面侧包层的背面侧粘合剂层（5）放置在背面（2b）上，其中制成大量V形槽（7） 在芯片（2）的表面（2a）和每个V形槽的相对端（7a，7b）中的恒定间隔暴露于片材的端面（2c，2d） 。 形成在各个槽（7）之间的芯片（2）的截面部分（8（2），8（4），...）用作光波导和剩余部分（8（1），8（3） ...），每个设置有跨越相邻的V形槽（7）延伸的V形槽（遮光槽）（9），用作非光波导。 因此可以在不使用光纤的情况下提供具有高精度地形成的光波导和非光波导的便宜且高度耐用的光卡（1）。
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公开(公告)号：US5210840A
公开(公告)日：1993-05-11
申请号：US412504
申请日：1989-09-26
CPC分类号： G06F9/342 , G06F12/0292
摘要： In a disclosed embodiment of the address space control apparatus, each general-purpose register usable as a base register is associated with another general-purpose register in addition to an access register containing a segment table origin. When a general-purpose register is selected as a base register, the contents of its associated general-purpose register are read out and added to the segment table origin from the associated access register to provide an effective segment table origin. In a modification, the access registers are omitted, and the general-purpose register selected as a base register are used to select an entry in a register or register array containing segment table origins in respective entries. In other embodiments disclosed, general-purpose registers are used in different manners to enhance virtual address space control functions.
摘要翻译： 在公开的地址空间控制装置的实施例中，除了包含段表原点的访问寄存器之外，可用作基址寄存器的每个通用寄存器与另一通用寄存器相关联。 当选择通用寄存器作为基址寄存器时，将相关联的通用寄存器的内容从相关的访问寄存器读出并添加到段表原点，以提供有效的段表原点。 在修改中，省略了访问寄存器，并且将用作基址寄存器的通用寄存器用于在相应条目中包含段表起始的寄存器或寄存器阵列中选择条目。 在所公开的其他实施例中，以不同的方式使用通用寄存器来增强虚拟地址空间控制功能。
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公开(公告)号：US5007005A
公开(公告)日：1991-04-09
申请号：US329556
申请日：1989-03-28
申请人： Yasuhiko Hatakeyama , Tomoo Aoyama
发明人： Yasuhiko Hatakeyama , Tomoo Aoyama
摘要： A data processing system capable of implementing at high speeds animating image generation processing and animating image display processing in synchronization with each other, thereby generating and displaying an animating image in a real time. The data processing system uses a given memory area of a storage unit as a screen buffer memory for storing an animating image data for each screen and is provided with an image processor for writing an animating image data for each screen in a screen buffer memory, an image display processor for reading the animating image data for from the screen buffer memory and for generating a display screen graphic signal to be supplied to a display unit and a hardware register circuit having a screen read-out control register corresponding to the animating image data for each screen of the screen buffer memory. The hardware register circuit updates data of the screen read-out control register in synchronization with each of a write operation of an animating image data from the image processor and a read operation of the animating image data to the image display processor. A delivery and a receipt of the data of the animating image data for each screen is carried out at high speeds between the image processor and the image display processor through the screen buffer memory storing the animating image data therefor by a control of the hardware register circuit.
摘要翻译： 一种数据处理系统，其能够高速实现图像生成处理和动画化图像显示处理，从而以实时的方式生成和显示动画图像。 数据处理系统使用存储单元的给定存储区作为用于存储每个屏幕的动画图像数据的屏幕缓冲存储器，并且设置有用于将每个屏幕的动画图像数据写入屏幕缓冲存储器的图像处理器， 图像显示处理器，用于从屏幕缓冲存储器读取动画图像数据，并产生要提供给显示单元的显示屏图形信号;以及具有与该动画图像数据对应的屏幕读出控制寄存器的硬件寄存器电路， 屏幕的每个屏幕缓冲存储器。 硬件寄存器电路与来自图像处理器的动画图像数据的写入操作以及动画图像数据的读取操作与图像显示处理器的读取操作同步地更新屏幕读出控制寄存器的数据。 在图像处理器和图像显示处理器之间通过屏幕缓冲存储器以高速度传送和接收每个屏幕的动画图像数据，通过硬件寄存器电路的控制来存储其动画图像数据 。
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公开(公告)号：US4658355A
公开(公告)日：1987-04-14
申请号：US449659
申请日：1982-12-14
IPC分类号： G06F7/00 , G06F9/38 , G06F15/78 , G06F17/16 , G06F15/347
CPC分类号： G06F15/8053 , G06F9/3867
摘要： In a pipeline arithmetic apparatus, an arithmetic operation is divided into a plurality of stages and processed in an overlapping manner in each of the stages. Arithmetic circuits are provided each in association with each stage. Registers hold control information indicating the contents of arithmetic operations to the individual arithmetic circuits or to a predetermined number of the arithmetic circuits, respectively. The control information held by each of the registers is supplied to the associated arithmetic circuit or circuits straight-forwardly or after having been decoded to command the arithmetic operation to be executed by each of the arithmetic circuits. The control information held by each of the registers as well as the output from each of the arithmetic circuits is transferred to the registers and the arithmetic circuits of the succeeding stages, respectively.
摘要翻译： 在流水线运算装置中，算术运算被划分为多个级，并且在每个级中以重叠的方式进行处理。 每个阶段都提供算术电路。 寄存器分别将表示算术运算内容的控制信息保存到各运算电路或预定数量的运算电路。 由每个寄存器保持的控制信息被直接提供给相关联的运算电路或解码之后，以指令由每个运算电路执行的算术运算。 每个寄存器保持的控制信息以及每个运算电路的输出分别被传送到后级的寄存器和运算电路。
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公开(公告)号：US4641275A
公开(公告)日：1987-02-03
申请号：US572521
申请日：1984-01-20
CPC分类号： G06F15/8084 , G06F9/30036
摘要： A vector processor has a main storage, a main memory control circuit, vector registers, data transfer circuits; an address register group, and vector arithmetic units. The vector processor performs vector arithmetic processings of vector data received from the vector registers and sends the results to the vector registers. For simple vector instructions, the vector processor divides the vector processings and carries out the vector processings in parallel, using a plurality of sets of the above-mentioned data transfer circuits, vector registers and vector arithmetic units. On the other hand, for complicated vector instructions, the vector processor carries out the vector processings without dividing them using the vector registers, data transfer circuits and vector arithmetic units which were designated by the vector instructions.
摘要翻译： 矢量处理器有一个主存储器，一个主存储器控制电路，向量寄存器，数据传输电路; 地址寄存器组和向量运算单元。 向量处理器执行从向量寄存器接收到的向量数据的向量运算处理，并将结果发送给向量寄存器。 对于简单的矢量指令，矢量处理器使用多组上述数据传送电路，矢量寄存器和矢量运算单元，分割向量处理并并行执行矢量处理。 另一方面，对于复杂的向量指令，向量处理器使用由向量指令指定的向量寄存器，数据传送电路和矢量运算单元来执行向量处理而不分割它们。
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