摘要:
An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor unit provides termination impedance to a transmission line connected to the external pin. The termination control unit varies the termination impedance in response to a plurality of bits of strength code associated with a data rate.
摘要:
An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor unit provides termination impedance to a transmission line connected to the external pin. The termination control unit varies the termination impedance in response to a plurality of bits of strength code associated with a data rate.
摘要:
A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal; determining one of the data pins to be a representative pin; performing clock and data recovery (CDR) on read data of the representative pin; and adjusting a phase of the data clock signal based on the CDR.
摘要:
A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal; determining one of the data pins to be a representative pin; performing clock and data recovery (CDR) on read data of the representative pin; and adjusting a phase of the data clock signal based on the CDR.
摘要:
A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit is configured to maintain oscillation of the oscillating unit. A bias current generating unit connected to the active element unit at a bias node provides a bias current to the bias node and is adapted to adjust the bias current in response to a control code. First and second capacitor blocks connected to the oscillating unit and the active element unit provide first and second load capacitances, respectively, to the first and second nodes, respectively, in response to the control code.
摘要:
A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit is configured to maintain oscillation of the oscillating unit. A bias current generating unit connected to the active element unit at a bias node provides a bias current to the bias node and is adapted to adjust the bias current in response to a control code. First and second capacitor blocks connected to the oscillating unit and the active element unit provide first and second load capacitances, respectively, to the first and second nodes, respectively, in response to the control code.
摘要:
An internal voltage generator includes a comparison unit, a driving circuit and a bias unit. The comparison unit compares a reference voltage and an internal voltage and is configured to output a comparison voltage, which is based on a difference between the reference voltage and the internal voltage. The driving circuit receives the comparison voltage and an external power supply voltage and is configured to output the internal voltage to an output node in response to the comparison voltage. The bias unit receives the internal voltage and is configured to adaptively adjust a bias current that flows through the bias unit to drive the comparison unit, in consideration of a level of the internal voltage.
摘要:
A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.