公开(公告)号：US20050028220A1

公开(公告)日：2005-02-03

申请号：US10791686

申请日：2004-03-03

申请人： David Baer ,  Jeff Tingley ,  Aleksandr Movshovich ,  Brad Grossman ,  Brian Schoner ,  Chengfuh Tang ,  Chuck Monahan ,  Darren Neuman ,  David Wu ,  Francis Cheung ,  Greg Kranawetter ,  Hoang Nhu ,  Hsien-Chih Tseng ,  Iue-Shuenn Chen ,  James Sweet ,  Jeffrey Bauch ,  Keith Klingler ,  Patrick Law ,  Rajesh Mamidwar ,  Dan Simon ,  Sang Tran ,  Shawn Johnson ,  Steven Jaffe ,  Thu Nguyen ,  Ut Nguyen ,  Yao-Hua Tseng ,  Brad Delanghe ,  Ben Giese ,  Jason Demas ,  Lakshman Ramakrishnan ,  Sandeep Bhatia ,  Guang-Ting Shih ,  Tracy Denk

发明人： David Baer ,  Jeff Tingley ,  Aleksandr Movshovich ,  Brad Grossman ,  Brian Schoner ,  Chengfuh Tang ,  Chuck Monahan ,  Darren Neuman ,  David Wu ,  Francis Cheung ,  Greg Kranawetter ,  Hoang Nhu ,  Hsien-Chih Tseng ,  Iue-Shuenn Chen ,  James Sweet ,  Jeffrey Bauch ,  Keith Klingler ,  Patrick Law ,  Rajesh Mamidwar ,  Dan Simon ,  Sang Tran ,  Shawn Johnson ,  Steven Jaffe ,  Thu Nguyen ,  Ut Nguyen ,  Yao-Hua Tseng ,  Brad Delanghe ,  Ben Giese ,  Jason Demas ,  Lakshman Ramakrishnan ,  Sandeep Bhatia ,  Guang-Ting Shih ,  Tracy Denk

IPC分类号： H04N5/44 ,  H04N5/445 ,  H04N5/46 ,  H04N5/913 ,  H04N7/035 ,  H04N3/27 ,  H04N7/173 ,  H04N11/06

CPC分类号： H04N21/426 ,  H04N5/4401 ,  H04N5/44504 ,  H04N5/46 ,  H04N7/035 ,  H04N21/4263 ,  H04N21/4305 ,  H04N2005/91364

摘要： A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

摘要翻译： 公开了一种提供用于在单个集成电路芯片上提供电视功能的成本有效方法的芯片上的电视（TVOC）系统。 TVOC包括以各种输入和输出格式接收和显示电视信号所必需的功能。 TVOC可用于有线和卫星电视的机顶盒，或直接在电视机内使用。 所提供的所有功能可以在单个集成电路上提供。 TVOC包括数据传输模块，IF解调器，数字音频引擎，模拟音频引擎，数字视频引擎和模拟视频引擎。 TVOC还包括三套接口，包括输出接口，控制接口和辅助接口。 其他特征和实施例提供增强的功能和提高的效率。

公开(公告)号：US20050036357A1

公开(公告)日：2005-02-17

申请号：US10641295

申请日：2003-08-15

申请人： Hoang Nhu ,  Jeffrey Bauch

发明人： Hoang Nhu ,  Jeffrey Bauch

IPC分类号： H04N5/44 ,  H04N5/46 ,  H04N5/913 ,  G11C11/00

CPC分类号： H04N21/426 ,  H04N5/4401 ,  H04N5/46 ,  H04N7/035 ,  H04N21/4263 ,  H04N2005/91364

摘要： A digital signal processor having a programmable address generator. In an embodiment, the programmable address generator enables an execution unit of the digital signal processor to perform register addressing, indirect addressing, and immediate addressing in response to a single arithmetic instruction. The digital signal processor is useful for implementing, for example, reprogrammable decoders and digital filters. In one embodiment, the digital signal processor is used to implement a US/Japan BTSC decoder.

摘要翻译： 一种具有可编程地址发生器的数字信号处理器。 在一个实施例中，可编程地址发生器使得数字信号处理器的执行单元响应于单个算术指令执行寄存器寻址，间接寻址和立即寻址。 数字信号处理器对于实现例如可编程解码器和数字滤波器是有用的。 在一个实施例中，数字信号处理器用于实现US / Japan BTSC解码器。

公开(公告)号：US07120203B2

公开(公告)日：2006-10-10

申请号：US10145411

申请日：2002-05-14

申请人： Jeffrey Bauch ,  Richard Berard ,  Christopher R. Pasqualino ,  Stephen G. Petilli

发明人： Jeffrey Bauch ,  Richard Berard ,  Christopher R. Pasqualino ,  Stephen G. Petilli

IPC分类号： H04L27/04

CPC分类号： G09G5/008 ,  G09G5/006 ,  H03L7/06 ,  H04L7/0008 ,  H04N21/42653

摘要： A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary link during dual link mode operations. The structure of the dual link transmitter includes both a primary link PLL and a secondary link PLL. The primary link PLL produces a primary link clock and the secondary link PLL produces a secondary link clock. During dual single link operations, the primary link clock is used to service the primary link while the secondary link clock is used to service the secondary link. However, during dual link operations, the primary link clock is used to service both the primary link and the secondary link.

摘要翻译： 根据本发明构造的双链路发射机在双链路模式操作期间采用单个锁相环（PLL）来服务主链路和辅链路。 双链路发射机的结构包括主链路PLL和辅助链路PLL。 主链路PLL产生主链路时钟，次链路PLL产生辅助链路时钟。 在双链路操作期间，主链路时钟用于为主链路服务，而辅链路时钟用于维护辅助链路。 然而，在双链路操作期间，主链路时钟用于为主链路和次链路服务。

公开(公告)号：US07254183B2

公开(公告)日：2007-08-07

申请号：US11516301

申请日：2006-09-05

申请人： Jeffrey Bauch ,  Richard Berard ,  Christopher R. Pasqualino ,  Stephen G. Petilli

发明人： Jeffrey Bauch ,  Richard Berard ,  Christopher R. Pasqualino ,  Stephen G. Petilli

IPC分类号： H04L27/04

CPC分类号： G09G5/008 ,  G09G5/006 ,  H03L7/06 ,  H04L7/0008 ,  H04N21/42653

摘要： A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary link during dual link mode operations. The structure of the dual link transmitter includes both a primary link PLL and a secondary link PLL. The primary link PLL produces a primary link clock and the secondary link PLL produces a secondary link clock. During dual single link operations, the primary link clock is used to service the primary link while the secondary link clock is used to service the secondary link. However, during dual link operations, the primary link clock is used to service both the primary link and the secondary link.

公开(公告)号：US20070002965A1

公开(公告)日：2007-01-04

申请号：US11516301

申请日：2006-09-05

申请人： Jeffrey Bauch ,  Richard Berard ,  Christopher Pasqualino ,  Stephen Petilli

发明人： Jeffrey Bauch ,  Richard Berard ,  Christopher Pasqualino ,  Stephen Petilli

IPC分类号： H04L27/00

CPC分类号： G09G5/008 ,  G09G5/006 ,  H03L7/06 ,  H04L7/0008 ,  H04N21/42653

摘要： A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary link during dual link mode operations. The structure of the dual link transmitter includes both a primary link PLL and a secondary link PLL. The primary link PLL produces a primary link clock and the secondary link PLL produces a secondary link clock. During dual single link operations, the primary link clock is used to service the primary link while the secondary link clock is used to service the secondary link. However, during dual link operations, the primary link clock is used to service both the primary link and the secondary link.

摘要翻译： 根据本发明构造的双链路发射机在双链路模式操作期间采用单个锁相环（PLL）来服务主链路和辅链路。 双链路发射机的结构包括主链路PLL和辅助链路PLL。 主链路PLL产生主链路时钟，次链路PLL产生辅助链路时钟。 在双链路操作期间，主链路时钟用于为主链路服务，而辅链路时钟用于维护辅助链路。 然而，在双链路操作期间，主链路时钟用于为主链路和次链路服务。