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    Data parallelizing receiver
    1.
    发明授权
    Data parallelizing receiver 有权
    数据并行接收器

    公开(公告)号：US08161349B2

    公开(公告)日：2012-04-17

    申请号：US12183552

    申请日：2008-07-31

    申请人： Hoe-Ju Chung ,  Joo-Sun Choi ,  Ken S. Lim

    发明人： Hoe-Ju Chung ,  Joo-Sun Choi ,  Ken S. Lim

    IPC分类号： H03M13/00

    CPC分类号： H03M13/091 ,  H03M13/6575

    摘要： Provided is a data parallelizing receiver including an input signal receiver for externally receiving serial data as packets, sampling the serial data, aligning the sampled data in an input order, and converting the aligned data into parallel data to output the parallel data, a cyclic redundancy check (CRC) partial calculator for receiving the parallel data, classifying the parallel data into groups according to the input order, and performing a partial CRC calculation on each of the groups to sequentially output a plurality of partial CRC calculation results, and a CRC partial calculation merger for receiving the plurality of partial CRC calculation results and merging the partial CRC calculation results to output CRC calculation data.

    摘要翻译： 提供了一种数据并行接收器，包括用于从外部接收串行数据作为分组的输入信号接收器，对串行数据进行采样，以输入顺序对准采样数据，并将对准的数据转换为并行数据以输出并行数据，循环冗余 检查（CRC）部分计算器，用于接收并行数据，根据输入顺序将并行数据分组成组，并对每个组执行部分CRC计算，以顺序输出多个部分CRC计算结果，以及CRC部分 用于接收多个部分CRC计算结果的计算合并，并将部分CRC计算结果合并到输出CRC计算数据。

    Memory system having low power consumption
    2.
    发明申请
    Memory system having low power consumption 失效
    具有低功耗的存储系统

    公开(公告)号：US20080177949A1

    公开(公告)日：2008-07-24

    申请号：US12006766

    申请日：2008-01-04

    申请人： Hoe-Ju Chung ,  Jung-Bae Lee ,  Joo-Sun Choi

    发明人： Hoe-Ju Chung ,  Jung-Bae Lee ,  Joo-Sun Choi

    IPC分类号： G06F12/08

    CPC分类号： G11C7/1075

    摘要： A memory system selectively sets signaling modes based on stack position information. The memory system includes a memory module having at least one semiconductor memory device and a memory controller configured to set a signaling mode based on stack position information of each of the semiconductor memory devices. A signaling between the memory controller and each of the semiconductor memory devices is performed in a differential signaling mode, and a signaling among the semiconductor memory devices is performed in a single-ended signaling mode. Accordingly, the memory system has reduced power consumption.

    摘要翻译： 存储器系统基于堆栈位置信息选择性地设置信令模式。 存储器系统包括具有至少一个半导体存储器件和存储器控制器的存储器模块，该存储器控制器被配置为基于每个半导体存储器件的堆叠位置信息设置信号模式。 在差分信令模式中执行存储器控制器和每个半导体存储器件之间的信令，并且以单端信令模式执行半导体存储器件之间的信令。 因此，存储系统具有降低的功耗。

    Memory system for controlling power and method thereof
    3.
    发明授权
    Memory system for controlling power and method thereof 有权
    用于控制电力的存储系统及其方法

    公开(公告)号：US07688666B2

    公开(公告)日：2010-03-30

    申请号：US11896123

    申请日：2007-08-29

    申请人： Joo-Sun Choi ,  Hoe-Ju Chung

    发明人： Joo-Sun Choi ,  Hoe-Ju Chung

    IPC分类号： G11C5/14

    CPC分类号： G06F1/3203 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    摘要： Example embodiments relate to a memory system and a method of controlling power thereof. The memory system may include a memory device and a memory controller. The memory device may be configured to be set to a specific power characteristic mode in response to a mode register set command so as to provide a power characteristic information corresponding to the specific power characteristic mode. The memory controller may be configured to provide the mode register set command to the memory device, configured to read the power characteristic information corresponding to the specific power characteristic mode from the memory device, configured to generate a power control information based on the power characteristic information, configured generate a command in response to the power control information, and provide the command to the memory device according to the power control information.

    摘要翻译： 示例性实施例涉及一种存储器系统及其功率控制方法。 存储器系统可以包括存储器设备和存储器控制器。 存储器件可以被配置为响应于模式寄存器设置命令被设置为特定功率特性模式，以便提供对应于特定功率特性模式的功率特性信息。 存储器控制器可以被配置为向存储器件提供模式寄存器设置命令，被配置为从存储器件读取与特定功率特性模式相对应的功率特性信息，其被配置为基于功率特性信息生成功率控制信息 配置为响应于功率控制信息生成命令，并且根据功率控制信息向存储器件提供命令。

    Memory system for controlling power and method thereof
    4.
    发明申请
    Memory system for controlling power and method thereof 有权
    用于控制电力的存储系统及其方法

    公开(公告)号：US20080059822A1

    公开(公告)日：2008-03-06

    申请号：US11896123

    申请日：2007-08-29

    申请人： Joo-Sun Choi ,  Hoe-Ju Chung

    发明人： Joo-Sun Choi ,  Hoe-Ju Chung

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3203 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    摘要： Example embodiments relate to a memory system and a method of controlling power thereof. The memory system may include a memory device and a memory controller. The memory device may be configured to be set to a specific power characteristic mode in response to a mode register set command so as to provide a power characteristic information corresponding to the specific power characteristic mode. The memory controller may be configured to provide the mode register set command to the memory device, configured to read the power characteristic information corresponding to the specific power characteristic mode from the memory device, configured to generate a power control information based on the power characteristic information, configured generate a command in response to the power control information, and provide the command to the memory device according to the power control information.

    摘要翻译： 示例性实施例涉及一种存储器系统及其功率控制方法。 存储器系统可以包括存储器设备和存储器控制器。 存储器件可以被配置为响应于模式寄存器设置命令被设置为特定功率特性模式，以便提供对应于特定功率特性模式的功率特性信息。 存储器控制器可以被配置为向存储器件提供模式寄存器设置命令，被配置为从存储器件读取与特定功率特性模式相对应的功率特性信息，其被配置为基于功率特性信息生成功率控制信息 配置为响应于功率控制信息生成命令，并且根据功率控制信息向存储器件提供命令。

    Memory system having low power consumption
    5.
    发明授权
    Memory system having low power consumption 失效
    具有低功耗的存储系统

    公开(公告)号：US07930492B2

    公开(公告)日：2011-04-19

    申请号：US12006766

    申请日：2008-01-04

    申请人： Hoe-Ju Chung ,  Jung-Bae Lee ,  Joo-Sun Choi

    发明人： Hoe-Ju Chung ,  Jung-Bae Lee ,  Joo-Sun Choi

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G11C7/1075

    摘要： A memory system selectively sets signaling modes based on stack position information. The memory system includes a memory module having at least one semiconductor memory device and a memory controller configured to set a signaling mode based on stack position information of each of the semiconductor memory devices. A signaling between the memory controller and each of the semiconductor memory devices is performed in a differential signaling mode, and a signaling among the semiconductor memory devices is performed in a single-ended signaling mode. Accordingly, the memory system has reduced power consumption.

    摘要翻译： 存储器系统基于堆栈位置信息选择性地设置信令模式。 存储器系统包括具有至少一个半导体存储器件和存储器控制器的存储器模块，该存储器控制器被配置为基于每个半导体存储器件的堆叠位置信息设置信号模式。 在差分信令模式中执行存储器控制器和每个半导体存储器件之间的信令，并且以单端信令模式执行半导体存储器件之间的信令。 因此，存储系统具有降低的功耗。

    Latency control circuit and method using queuing design method
    7.
    发明授权
    Latency control circuit and method using queuing design method 失效
    延迟控制电路和使用排队设计方法的方法

    公开(公告)号：US08230140B2

    公开(公告)日：2012-07-24

    申请号：US13178846

    申请日：2011-07-08

    申请人： Byung-Hoon Jeong ,  Hoe-Ju Chung

    发明人： Byung-Hoon Jeong ,  Hoe-Ju Chung

    IPC分类号： G06F3/00

    CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/109 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272

    摘要： A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

    摘要翻译： 等待时间控制电路包括FIFO控制器和寄存器单元。 FIFO控制器可以根据外部命令生成增加信号，并根据内部命令生成减少信号。 FIFO控制器还可以响应于增加信号和减小信号启用深度点信号。 寄存器单元可以包括n个寄存器。 值n（四舍五入）可以通过将最大数量的加性延迟和最大写入延迟数的较大值除以列周期延迟时间（tCCD）来获得。 寄存器可以响应于增加信号和时钟信号而存储与外部命令接收的地址，并且可以将地址或先前地址移位到相邻寄存器。 延迟控制电路将存储在寄存器中的地址作为与启用的深度点信号相对应的列地址。

    System and device with error detection/correction process and method outputting data
    8.
    发明授权
    System and device with error detection/correction process and method outputting data 有权
    具有错误检测/校正处理和方法输出数据的系统和设备

    公开(公告)号：US08112680B2

    公开(公告)日：2012-02-07

    申请号：US12044183

    申请日：2008-03-07

    申请人： Hoe-Ju Chung ,  Jung-Bae Lee

    发明人： Hoe-Ju Chung ,  Jung-Bae Lee

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1008 ,  G11C5/02 ,  G11C5/04 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1045 ,  G11C2029/0411 ,  H04L1/0041 ,  H04L1/0057

    摘要： A system, device and related method are used to communicate data via a plurality of data lanes including a selected data lane. In a first mode of operation, payload data and related supplemental data are communicated via the plurality of data lanes including the selected data lane. In a second mode of operation, only payload data is communicated via the plurality of data lanes, except the selected data lane.

    摘要翻译： 系统，设备和相关方法用于经由包括所选择的数据通道的多个数据通道来传送数据。 在第一操作模式中，经由包括所选择的数据通道的多个数据通道来传送有效载荷数据和相关的补充数据。 在第二种操作模式中，只有有效载荷数据经由多个数据通道被传送，除了所选择的数据通道。

    Semiconductor device having ESD protection circuit and method of testing the same
    10.
    发明申请
    Semiconductor device having ESD protection circuit and method of testing the same 有权
    具有ESD保护电路的半导体器件及其测试方法

    公开(公告)号：US20090085599A1

    公开(公告)日：2009-04-02

    申请号：US12232592

    申请日：2008-09-19

    申请人： Young-Don Choi ,  Hoe-Ju Chung

    发明人： Young-Don Choi ,  Hoe-Ju Chung

    IPC分类号： G01R31/26 ,  H01L23/60

    CPC分类号： G01R31/2884 ,  H01L23/60 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device having an electrostatic discharge (ESD) protection circuit and a method of testing the same may provided. The semiconductor device may include one or more stacked chips, each stacked chip may include a test circuit configured to output a test control signal and a selection control signal in response to a test enable signal, an internal circuit configured to perform an operation and output a plurality of test signals in response to the test control signal, at least one multiplexer (MUX) configured to select and output one of the plurality of test signals based on the selection control signal, at least one test pad configured to receive the selected test signal, and at least one electrostatic discharge (ESD) protection circuit configured to discharge static electricity applied through the test pad externally.

    摘要翻译： 可以提供具有静电放电（ESD）保护电路的半导体器件及其测试方法。 半导体器件可以包括一个或多个堆叠的芯片，每个堆叠的芯片可以包括测试电路，其被配置为响应于测试使能信号输出测试控制信号和选择控制信号，内部电路被配置为执行操作并输出 响应于测试控制信号的多个测试信号，至少一个多路复用器（MUX），被配置为基于选择控制信号选择并输出多个测试信号中的一个;至少一个测试板，被配置为接收所选择的测试信号 以及至少一个静电放电（ESD）保护电路，其被配置为从外部排出通过测试焊盘施加的静电。