摘要:
Semiconductor devices and methods of forming devices that have field oxides in trenches are disclosed. According to the methods, a semiconductor substrate is prepared. An upper trench is formed at a predetermined region of the semiconductor substrate and a bottom trench is formed at a bottom surface of the upper trench. A field oxide is formed to fill the bottom trench and the upper trench. At this time, the upper trench has a wider width than the bottom trench.
摘要:
Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region. Accordingly, it can minimize a depth of recessed regions (dent regions) to be formed at edge regions of the first isolation layer during removal of the pad insulation layer, and it can prevent dent regions from being formed at edge regions of the second isolation layer.
摘要:
A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.
摘要:
NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.
摘要:
NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.
摘要:
A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.
摘要:
A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.
摘要:
A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.
摘要:
A non-volatile memory cell array having second floating gates with a narrow width, a large height, and slanted side walls. Critical dimension errors due to photolithographic and etching processes are decreased. The difference in the coupling ratio between the memory cells is low thereby improving speed during programming and/or erasing. A second floating gate having a narrower critical dimension than a second floating gate obtained using a photolithographic process may be designed, thereby forming a highly integrated non-volatile memory cell array.
摘要:
A non-volatile memory device and fabrication methods thereof are provided. A first inter-gate insulating layer is formed to intervene between control gate electrodes and floating gate electrodes in a cell array area. A second inter-gate insulating layer is formed to intervene between a gate electrode and a dummy gate electrode in a peripheral circuit area. The second inter-gate insulating layer has a thickness greater than a thickness of the first inter-gate insulating layer on a top surface of the floating gate electrodes. By reducing the difference between the thickness of the first inter-gate insulating layer on sidewalls of floating gate patterns and the thickness of the second inter-gate insulating layer on a gate electrode pattern, in accordance with the invention, any etching damage to the substrate in the peripheral circuit area can be considerably reduced or prevented during the fabrication process.