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1.发明申请公开(公告)号：US20160188305A1
公开(公告)日：2016-06-30
申请号：US14583657
申请日：2014-12-27
申请人： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Arthur N. Glew , Paul M. PetersEn , Victor W. Lee , P.G. Lowney , Arch D. Robinson , Cheng Wang
发明人： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Arthur N. Glew , Paul M. PetersEn , Victor W. Lee , P.G. Lowney , Arch D. Robinson , Cheng Wang
摘要： Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.
摘要翻译： 用于生成可组合库函数的技术包括：第一计算设备，其包括被配置为编译可组合库的库编译器和第二计算设备，所述第二计算设备包括应用编译器，所述应用编译器被配置为基于以不同级别写入的多个抽象来组合所述可组合库的库函数 的抽象。 例如，抽象可以包括高级别的算法抽象，中等级别的阻塞算法抽象，以及低级别的基于区域的代码抽象。 在此描述和要求保护的其它实施例。
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公开(公告)号：US20140176590A1
公开(公告)日：2014-06-26
申请号：US14054933
申请日：2013-10-16
申请人： Victor W. Lee , Mikhail Smelyanskiy , Ganesh S. Dasika , Jose Gonzalez , Jatin Chhugani , Yen-Kuang Chen , Changkyu Kim , Julio Gago , Santiago Galan , Victor Moya Del Barrio
发明人： Victor W. Lee , Mikhail Smelyanskiy , Ganesh S. Dasika , Jose Gonzalez , Jatin Chhugani , Yen-Kuang Chen , Changkyu Kim , Julio Gago , Santiago Galan , Victor Moya Del Barrio
CPC分类号： G06T11/001 , G06F17/16 , G06T1/00
摘要： A texture unit may be used to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.
摘要翻译： 纹理单元可用于执行诸如点积的通用数学计算。 这使得一些通用计算和操作能够从中央处理单元卸载到纹理单元。 纹理单元可以使用线性内插器来执行点积计算。
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公开(公告)号：US20130332701A1
公开(公告)日：2013-12-12
申请号：US13996521
申请日：2011-12-23
申请人： Jayashankar Bharadwaj , Nalini Vasudevan , Victor W. Lee , Daehyun Kim , Albert Hartono , Sara S. Baghsorkhi
发明人： Jayashankar Bharadwaj , Nalini Vasudevan , Victor W. Lee , Daehyun Kim , Albert Hartono , Sara S. Baghsorkhi
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/30018 , G06F9/30036
摘要： An apparatus and method are described for selecting elements to be used in a vector computation. For example, a method according to one embodiment includes the following operations: specifying whether to identify the first, last or next after last active element of an input mask register using an immediate value; identifying the first, last or next after last active element in the input mask register according to the immediate value; reading a value from an input vector register corresponding to the identified first, last or next after last active element in the input mask register; and writing the value to an output vector register.
摘要翻译： 描述了用于选择要在向量计算中使用的元素的装置和方法。 例如，根据一个实施例的方法包括以下操作：使用立即值来指定是否识别输入屏蔽寄存器的第一，最后或下一个有效元素; 根据立即值识别输入屏蔽寄存器中的最后一个或最后一个有效元素; 从输入矢量寄存器读取对应于输入屏蔽寄存器中识别的第一，最后或下一个最后有效元件的值; 并将该值写入输出向量寄存器。
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公开(公告)号：US08570336B2
公开(公告)日：2013-10-29
申请号：US12633062
申请日：2009-12-08
申请人： Victor W. Lee , Mikhail Smelyanskiy , Ganesh S. Dasika , Jose Gonzalez , Jatin Chhugani , Yen-Kuang Chen , Changkyu Kim , Julio Gago , Santiago Galan , Victor Moya Del Barrio
发明人： Victor W. Lee , Mikhail Smelyanskiy , Ganesh S. Dasika , Jose Gonzalez , Jatin Chhugani , Yen-Kuang Chen , Changkyu Kim , Julio Gago , Santiago Galan , Victor Moya Del Barrio
IPC分类号： G09G5/00
CPC分类号： G06T11/001 , G06F17/16 , G06T1/00
摘要： A texture unit may be used utilized to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.
摘要翻译： 可以使用纹理单元来执行诸如点积的通用数学计算。 这使得一些通用计算和操作能够从中央处理单元卸载到纹理单元。 纹理单元可以使用线性内插器来执行点积计算。
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5.发明申请METHOD AND SYSTEM FOR FLEXIBLE AND NEGOTIABLE EXCHANGE OF LINK LAYER FUNCTIONAL PARAMETERS 有权链路层功能参数的灵活和可交换的方法和系统公开(公告)号：US20090064179A1
公开(公告)日：2009-03-05
申请号：US12242257
申请日：2008-09-30
IPC分类号： G06F9/46
CPC分类号： G06F13/423
摘要： A proposal is discussed that facilitates exchanging parameters for a link layer that allows a variable number of parameters without changing a communication protocol. Likewise, the proposal allows for both components connected via the link to negotiate values for the parameters that are exchanged without a need for external agent intervention or redundancy.
摘要翻译： 讨论了一种促进交换参数的方案，该参数允许可变数量的参数而不改变通信协议。 同样，该建议允许通过链路连接的两个组件协商交换的参数的值，而不需要外部代理干预或冗余。
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6.发明授权公开(公告)号：US07484014B2
公开(公告)日：2009-01-27
申请号：US11238491
申请日：2005-09-28
IPC分类号： G06F3/00
CPC分类号： G06F13/423
摘要： A proposal is discussed that facilitates exchanging parameters for a link layer that allows a variable number of parameters without changing a communication protocol. Likewise, the proposal allows for both components connected via the link to negotiate values for the parameters that are exchanged without a need for external agent intervention or redundancy.
摘要翻译： 讨论了一种促进交换参数的方案，该参数允许可变数量的参数而不改变通信协议。 同样，该建议允许通过链路连接的两个组件协商交换的参数的值，而不需要外部代理干预或冗余。
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7.发明申请APPARATUS AND METHOD FOR PROPAGATING CONDITIONALLY EVALUATED VALUES IN SIMD/VECTOR EXECUTION 有权在SIMD / VECTOR执行中传播有条件评估值的装置和方法公开(公告)号：US20140189323A1
公开(公告)日：2014-07-03
申请号：US13997183
申请日：2011-12-23
申请人： Jayashankar Bharadwaj , Nalini Vasudevan , Victor W. Lee , Daehyun Kim , Albert Hartono , Sara S. Baghsorkhi
发明人： Jayashankar Bharadwaj , Nalini Vasudevan , Victor W. Lee , Daehyun Kim , Albert Hartono , Sara S. Baghsorkhi
IPC分类号： G06F9/30
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30098 , G06F9/30192 , G06F9/3877
摘要： An apparatus and method for propagating conditionally evaluated values. For example, a method according to one embodiment comprises: reading each value contained in an input mask register, each value being a true value or a false value and having a bit position associated therewith; for each true value read from the input mask register, generating a first result containing the bit position of the true value; for each false value read from the input mask register following the first true value, adding the vector length of the input mask register to a bit position of the last true value read from the input mask register to generate a second result; and storing each of the first results and second results in bit positions of an output register corresponding to the bit positions read from the input mask register.
摘要翻译： 用于传播有条件评估值的装置和方法。 例如，根据一个实施例的方法包括：读取输入屏蔽寄存器中包含的每个值，每个值是真值或假值，并具有与其相关联的位位置; 对于从输入掩码寄存器读取的每个真值，生成包含真值的位位置的第一结果; 对于从输入屏蔽寄存器读取的每个错误值跟随第一个真实值，将输入屏蔽寄存器的向量长度加到从输入屏蔽寄存器读取的最后一个真值的位位置，以产生第二个结果; 并将每个第一结果和第二结果存储在与从输入屏蔽寄存器读取的位位置对应的输出寄存器的位位置中。
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8.发明申请公开(公告)号：US20140149718A1
公开(公告)日：2014-05-29
申请号：US13687918
申请日：2012-11-28
IPC分类号： G06F9/38
CPC分类号： G06F9/30043 , G06F9/30036 , G06F9/30185 , G06F9/3834 , G06F9/3851 , G06F9/3887 , G06F9/544 , G06F12/0815 , G06F12/084 , G06F12/0875 , G06F2212/452 , G06F2212/60 , G06F2212/621 , Y02D10/13
摘要： Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.
摘要翻译： 说明和逻辑提供推送缓冲区复制和存储功能。 一些实施例包括第一硬件线程或处理核心，以及第二硬件线程或处理核心，高速缓存，用于存储由第二硬件线程或处理核心可访问的共享存储器地址的高速缓存行中的高速缓存相干数据。 响应于对指定源数据操作数，所述共享存储器地址作为目的地操作数的指令以及所述共享存储器地址的一个或多个所有者进行解码，一个或多个执行单元将数据从源数据操作数复制到高速缓存一致数据 当所述一个或多个所有者包括所述第二硬件线程或处理核心时，由所述第二硬件线程或高速缓存中的处理核心访问的所述共享存储器地址的高速缓存行。
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公开(公告)号：US08478941B2
公开(公告)日：2013-07-02
申请号：US13557164
申请日：2012-07-24
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
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公开(公告)号：US20120290799A1
公开(公告)日：2012-11-15
申请号：US13557164
申请日：2012-07-24
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
摘要翻译： 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。
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