公开(公告)号：US07826563B2

公开(公告)日：2010-11-02

申请号：US11717262

申请日：2007-03-13

申请人： Hongming An ,  Simon Pang ,  Viet Linh Do

发明人： Hongming An ,  Simon Pang ,  Viet Linh Do

IPC分类号： H03D3/24

CPC分类号： H03L7/193 ,  G06F7/68 ,  H03K23/68

摘要： A system and method are provided for multi-modulus division. The method accepts an input first signal having a first frequency and divides the first frequency by an integral number. A second signal is generated with a plurality of phase outputs, each having a second frequency. Using a daisy-chain register controller, phase outputs are selected and supplied as a third signal with a frequency. Selecting phase outputs using the daisy-chain register controller includes supplying the third signal as a clock signal to registers having outputs connected in a daisy-chain. Then, a sequence of register output pulses is generated in response to the clock signals, and register output pulses are chosen from the sequence to select second signal phase outputs. By using 8-second signal phase outputs, a third signal is obtained with a frequency equal to the second frequency multiplied by one of the following numbers: 0.75, 0.875, 1, 1.125, or 1.25.

摘要翻译： 提供了一种用于多模式分割的系统和方法。 该方法接受具有第一频率的输入第一信号，并将第一频率除以整数。 利用具有第二频率的多个相位输出产生第二信号。 使用菊花链寄存器控制器，相位输出被选择并作为具有频率的第三个信号提供。 使用菊花链寄存器控制器选择相位输出包括将第三个信号作为时钟信号提供给具有以菊花链连接的输出的寄存器。 然后，响应于时钟信号产生寄存器输出脉冲序列，并且从序列中选择寄存器输出脉冲以选择第二信号相位输出。 通过使用8秒信号相位输出，获得第三个信号，频率等于第二个频率乘以以下数字之一：0.75,0.875,1,1125或1.25。

公开(公告)号：US20080225989A1

公开(公告)日：2008-09-18

申请号：US11717262

申请日：2007-03-13

申请人： Hongming An ,  Simon Pang ,  Viet Linh Do

发明人： Hongming An ,  Simon Pang ,  Viet Linh Do

IPC分类号： H04L27/00

CPC分类号： H03L7/193 ,  G06F7/68 ,  H03K23/68

摘要： A system and method are provided for multi-modulus division. The method accepts an input first signal having a first frequency and divides the first frequency by an integral number. A second signal is generated with a plurality of phase outputs, each having a second frequency. Using a daisy-chain register controller, phase outputs are selected and supplied as a third signal with a frequency. Selecting phase outputs using the daisy-chain register controller includes supplying the third signal as a clock signal to registers having outputs connected in a daisy-chain. Then, a sequence of register output pulses is generated in response to the clock signals, and register output pulses are chosen from the sequence to select second signal phase outputs. By using 8-second signal phase outputs, a third signal is obtained with a frequency equal to the second frequency multiplied by one of the following numbers: 0.75, 0.875, 1, 1.125, or 1.25.

摘要翻译： 提供了一种用于多模式分割的系统和方法。 该方法接受具有第一频率的输入第一信号，并将第一频率除以整数。 利用具有第二频率的多个相位输出产生第二信号。 使用菊花链寄存器控制器，相位输出被选择并作为具有频率的第三个信号提供。 使用菊花链寄存器控制器选择相位输出包括将第三个信号作为时钟信号提供给具有以菊花链连接的输出的寄存器。 然后，响应于时钟信号产生寄存器输出脉冲序列，并且从序列中选择寄存器输出脉冲以选择第二信号相位输出。 通过使用8秒信号相位输出，获得第三个信号，频率等于第二个频率乘以以下数字之一：0.75,0.875,1,1125或1.25。

公开(公告)号：US20080224735A1

公开(公告)日：2008-09-18

申请号：US12120027

申请日：2008-05-13

申请人： Viet Linh Do ,  Simon Pang ,  Hongming An ,  Jim Lew

发明人： Viet Linh Do ,  Simon Pang ,  Hongming An ,  Jim Lew

IPC分类号： H03B21/00

CPC分类号： H03L7/1976 ,  G06F7/68 ,  H03K23/486

摘要： A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q

摘要翻译： 提供了一种使用合理划分来合成信号频率的系统和方法。 该方法接受参考频率值和合成频率值。 响应于将合成频率值除以参考频率值，确定整数值分子（dp）和整数值分母（dq）。 该方法降低了dp / dq与整数N的比值和p / q（dp / dq = N（p / q））的比值，其中p / q <1（十进制）。 分子（p）和分母（q）被提供给灵活的累加器模块，因此产生除数。 N与k位商相加以创建除数。 在锁相环（PLL）中，除数和参考信号用于产生频率等于合成频率值的合成信号。

公开(公告)号：US08443023B2

公开(公告)日：2013-05-14

申请号：US12120027

申请日：2008-05-13

申请人： Viet Linh Do ,  Simon Pang ,  Hongming An ,  Jim Lew

发明人： Viet Linh Do ,  Simon Pang ,  Hongming An ,  Jim Lew

IPC分类号： G06F1/02

CPC分类号： H03L7/1976 ,  G06F7/68 ,  H03K23/486

摘要： A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q

摘要翻译： 提供了一种使用合理划分来合成信号频率的系统和方法。 该方法接受参考频率值和合成频率值。 响应于将合成频率值除以参考频率值，确定整数值分子（dp）和整数值分母（dq）。 该方法降低了dp / dq与整数N的比值和p / q（dp / dq = N（p / q））的比率，其中p / q <1（十进制）。 分子（p）和分母（q）被提供给灵活的累加器模块，因此产生除数。 N与k位商相加以创建除数。 在锁相环（PLL）中，除数和参考信号用于产生频率等于合成频率值的合成信号。

公开(公告)号：US08094754B2

公开(公告)日：2012-01-10

申请号：US12327776

申请日：2008-12-03

申请人： Mehmet Mustafa Eker ,  Simon Pang ,  Viet Linh Do ,  Hongming An ,  Philip Michael Clovis

发明人： Mehmet Mustafa Eker ,  Simon Pang ,  Viet Linh Do ,  Hongming An ,  Philip Michael Clovis

IPC分类号： H03D3/24

CPC分类号： H04L7/033 ,  H03L7/087 ,  H03L7/10 ,  H03L7/1976 ,  H03L7/22

摘要： A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency. Using a rotational frequency detector (RFD), the second communication signal, and the second synthesized signal, a second synthesized signal is generated having an output frequency equal to second frequency.

摘要翻译： 提供了一种用于在时钟和数据恢复（CDR）设备频率合成器中保持非同步通信信号的频率的系统和方法。 该方法最初获取具有第一频率的非同步第一通信信号的相位，并且将第一合成信号除以所选频率比值，产生频率等于参考信号频率的频率检测信号。 响应于丢失第一通信信号并随后接收具有非预定第二频率的第二通信信号，基于第二频率相同或接近第一频率的假设，从存储器检索频率比值。 使用相位频率检测器（PFD），参考信号和频率比值，产生具有等于第一频率的输出频率的第二合成信号。 使用旋转频率检测器（RFD），第二通信信号和第二合成信号，生成具有等于第二频率的输出频率的第二合成信号。

公开(公告)号：US20090147901A1

公开(公告)日：2009-06-11

申请号：US12372946

申请日：2009-02-18

申请人： Viet Linh Do ,  Philip Michael Clovis ,  Michael Hellmer ,  Mehmet Mustafa Eker ,  Hongming An ,  Simon Pang

发明人： Viet Linh Do ,  Philip Michael Clovis ,  Michael Hellmer ,  Mehmet Mustafa Eker ,  Hongming An ,  Simon Pang

IPC分类号： H04L7/00

CPC分类号： H04L7/0331 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/113 ,  H03L7/1976 ,  H04L7/0004

摘要： A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired.

摘要翻译： 提供了一种用于时钟和数据恢复（CDR）设备中的自动频率采集维护的系统和方法。 在自动频率采集（AFA）模式中，该方法使用相位检测器（PHD）来获取具有初始第一频率的非同步输入通信信号的相位。 在信号失去锁定/丢失（LOL / LOS）信号被断言的情况下，从存储器检索频率比值。 使用相位频率检测器（PFD），参考信号和频率比值，产生合成信号。 响应于使用PFD产生合成信号并且LOL / LOS信号被无效，旋转频率检测器（RFD）用于产生具有等于输入通信信号频率的频率的合成信号。 随着LOL / LOS信号的持续消除，PHD被使能，并且获取输入信号的相位。

公开(公告)号：US20090092213A1

公开(公告)日：2009-04-09

申请号：US12327776

申请日：2008-12-03

申请人： Mehmet Mustafa Eker ,  Simon Pang ,  Viet Linh Do ,  Hongming An ,  Philip Michael Clovis

发明人： Mehmet Mustafa Eker ,  Simon Pang ,  Viet Linh Do ,  Hongming An ,  Philip Michael Clovis

IPC分类号： H04L7/04

CPC分类号： H04L7/033 ,  H03L7/087 ,  H03L7/10 ,  H03L7/1976 ,  H03L7/22

摘要： A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency. Using a rotational frequency detector (RFD), the second communication signal, and the second synthesized signal, a second synthesized signal is generated having an output frequency equal to second frequency.

摘要翻译： 提供了一种用于在时钟和数据恢复（CDR）设备频率合成器中保持非同步通信信号的频率的系统和方法。 该方法最初获取具有第一频率的非同步第一通信信号的相位，并且将第一合成信号除以所选频率比值，产生频率等于参考信号频率的频率检测信号。 响应于丢失第一通信信号并随后接收具有非预定第二频率的第二通信信号，基于第二频率相同或接近第一频率的假设，从存储器检索频率比值。 使用相位频率检测器（PFD），参考信号和频率比值，产生具有等于第一频率的输出频率的第二合成信号。 使用旋转频率检测器（RFD），第二通信信号和第二合成信号，生成具有等于第二频率的输出频率的第二合成信号。

公开(公告)号：US08111785B2

公开(公告)日：2012-02-07

申请号：US12372946

申请日：2009-02-18

申请人： Viet Linh Do ,  Philip Michael Clovis ,  Michael Hellmer ,  Mehmet Mustafa Eker ,  Hongming An ,  Simon Pang

发明人： Viet Linh Do ,  Philip Michael Clovis ,  Michael Hellmer ,  Mehmet Mustafa Eker ,  Hongming An ,  Simon Pang

IPC分类号： H03D3/18 ,  H03D3/24 ,  H04L7/00

CPC分类号： H04L7/0331 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/113 ,  H03L7/1976 ,  H04L7/0004

摘要： A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired.

摘要翻译： 提供了一种用于时钟和数据恢复（CDR）设备中的自动频率采集维护的系统和方法。 在自动频率采集（AFA）模式中，该方法使用相位检测器（PHD）来获取具有初始第一频率的非同步输入通信信号的相位。 在信号失去锁定/丢失（LOL / LOS）信号被断言的情况下，从存储器检索频率比值。 使用相位频率检测器（PFD），参考信号和频率比值，产生合成信号。 响应于使用PFD产生合成信号并且LOL / LOS信号被无效，旋转频率检测器（RFD）用于产生具有等于输入通信信号频率的频率的合成信号。 随着LOL / LOS信号的持续消除，PHD被使能，并且获取输入信号的相位。

公开(公告)号：US08121242B2

公开(公告)日：2012-02-21

申请号：US12388024

申请日：2009-02-18

申请人： Viet Linh Do ,  Mehmet Mustafa Eker ,  Simon Pang

发明人： Viet Linh Do ,  Mehmet Mustafa Eker ,  Simon Pang

IPC分类号： H03D3/24

CPC分类号： H04L7/0004 ,  H03L7/0891 ,  H03L7/113 ,  H03L7/1976 ,  H04L7/033

摘要： A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO is selected. Using a phase-locked loop (PLL) and the initial VCO, the frequency of the input communication signal is acquired and the acquired signal tuning voltage of the initial VCO is measured. Then, the initial VCO is disengaged and a plurality of adjacent band VCOs is sequentially engaged. The acquired signal tuning voltage of each VCO is measured and a final VCO is selected that is able to generate the input communication signal frequency using an acquired signal tuning voltage closest to a midpoint of a predetermined tuning voltage range.

摘要翻译： 提供了一种用于使用重叠压控振荡器（VCO）频带的接收机中的频率锁定稳定性的系统和方法。 接受输入通信信号并选择初始VCO。 使用锁相环（PLL）和初始VCO，获取输入通信信号的频率，并测量初始VCO的采集信号调谐电压。 然后，初始VCO被分离并且多个相邻频带VCO被顺序地接合。 测量每个VCO的获取的信号调谐电压，并且选择能够使用最接近预定调谐电压范围的中点的获取的信号调谐电压来产生输入通信信号频率的最终VCO。

公开(公告)号：US07936853B2

公开(公告)日：2011-05-03

申请号：US11983675

申请日：2007-11-09

申请人： Simon Pang ,  Viet Linh Do ,  Mehmet Mustafa Eker

发明人： Simon Pang ,  Viet Linh Do ,  Mehmet Mustafa Eker

IPC分类号： H04L7/00

CPC分类号： H04L7/0083 ,  H03L7/095 ,  H03L2207/14 ,  Y10S331/02

摘要： A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge transitions in the raw data signal, creating a raw count. A clock signal is also accepted at a second rate. The clock signal is a timing reference recovered from the raw data signal. The raw data signal is sampled at a rate responsive to the clock signal, generating a sampled signal. Edge transitions are counted in the sampled signal, creating a sampled count. Then, the raw count is compared to the sampled count, to determine if the first rate is equal to the second rate. The method is used to determine if the second rate is less than the first rate—to detect if the clock signal is incorrectly locked to the first rate.

摘要翻译： 提供了用于检测时钟和数据恢复（CDR）设备中的假时钟频率锁定的系统和方法。 该方法以第一速率接收数字原始数据信号，并计算原始数据信号中的边沿转换，创建原始计数。 时钟信号也以第二速率被接受。 时钟信号是从原始数据信号恢复的定时参考。 原始数据信号以响应于时钟信号的速率被采样，产生采样信号。 在采样信号中计数边沿转换，创建采样计数。 然后，将原始计数与采样计数进行比较，以确定第一速率是否等于第二速率。 该方法用于确定第二速率是否小于第一速率 - 以检测时钟信号是否被错误地锁定到第一速率。