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1.发明授权Method and system for characterizing coupling capacitance between integrated circuit interconnects 失效表征集成电路互连之间的耦合电容的方法和系统公开(公告)号：US06333680B1
公开(公告)日：2001-12-25
申请号：US09677348
申请日：2000-10-02
IPC分类号： H03B524
CPC分类号： G01R27/2605 , G01R31/04
摘要： An exemplary embodiment of the invention is a method of characterizing capacitances of a plurality of integrated circuit interconnects. The method includes coupling a first oscillator to a first integrated circuit interconnect and coupling a second oscillator to a second integrated circuit interconnect. The first oscillator is activated to characterize the sum of (i) coupling capacitance between the first integrated-circuit interconnect and the second integrated-circuit interconnect and (ii) ground capacitance between the first integrated-circuit interconnect and a ground. In addition, both of the first oscillator and the second oscillator are activated to characterize the ground capacitance between the first integrated-circuit interconnect and the ground.
摘要翻译： 本发明的示例性实施例是表征多个集成电路互连的电容的方法。 该方法包括将第一振荡器耦合到第一集成电路互连并将第二振荡器耦合到第二集成电路互连。 激活第一振荡器以表征（i）第一集成电路互连和第二集成电路互连之间的耦合电容和（ii）第一集成电路互连和地之间的接地电容之和的和。 此外，第一振荡器和第二振荡器都被激活以表征第一集成电路互连和地之间的接地电容。
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公开(公告)号：US4851711A
公开(公告)日：1989-07-25
申请号：US151381
申请日：1988-02-02
摘要： An asymmetrical delay generator for use in a clock chopping circuit is disclosed. The circuit has a complementary transistor switch memory cell in it. That cell is operated in a mode where one half of the cell operates in saturation mode. That half of the cell controls the pulse width of the chopper. The other half of the cell is not operated in saturation and controls the resetting of the chopper and hence the maximum clock rate at which the circuit will operate.
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