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公开(公告)号：US08987700B2
公开(公告)日：2015-03-24
申请号：US13310583
申请日：2011-12-02
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A memory device includes a plurality of side-wall electrodes formed on a first side-wall of a trench within an insulating layer over a first plurality of contacts in an array of contacts in a substrate. The plurality of side-wall electrodes contact respective top surfaces of the first plurality of contacts. The side-wall electrodes respectively comprise a layer of tantalum nitride, having a composition TaxNy, where y is greater than x, and a layer of electrode material having a lower electrical resistivity and a lower thermal resistivity than the layer of tantalum nitride. Top surfaces of the plurality of side-wall electrodes contact memory material. A second plurality of side-wall electrodes may be formed on a second side-wall of the trench over a second plurality of contacts in the array of contacts.
摘要翻译： 存储器件包括多个侧壁电极，形成在绝缘层中的沟槽的第一侧壁上，在衬底中的触点阵列中的第一多个触点上。 多个侧壁电极接触第一多个触点的相应顶表面。 侧壁电极分别包括氮化钽层，其具有组成为TaxNy，其中y大于x，并且电极材料层具有比氮化钽层更低的电阻率和更低的热阻率。 多个侧壁电极的顶表面接触记忆材料。 第二多个侧壁电极可以形成在沟槽阵列中的第二多个触点上的沟槽的第二侧壁上。
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2.发明授权公开(公告)号：US08933536B2
公开(公告)日：2015-01-13
申请号：US12357912
申请日：2009-01-22
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Chung H. Lam , Bipin Rajendran
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Chung H. Lam , Bipin Rajendran
IPC分类号： H01L27/082 , H01L27/102 , H01L27/24 , H01L45/00
CPC分类号： H01L27/1026 , H01L27/2445 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1625 , H01L45/1683
摘要： Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter.
摘要翻译： 本文描述了具有与双极结晶体管存取装置的发射极自对准的存储元件的存储单元以及用于制造这种装置的方法。 如本文所述的存储器件包括多个存储器单元。 多个存储单元中的存储单元包括双极结型晶体管，其包括由掺杂多晶硅柱构成的发射极。 存储单元包括在发射器上的绝缘元件，并且具有延伸穿过绝缘层的开口，开口以发射器为中心。 存储单元还包括在开口内的存储元件并电耦合到发射器。
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公开(公告)号：US08829646B2
公开(公告)日：2014-09-09
申请号：US12430290
申请日：2009-04-27
申请人： Hsiang-Lan Lung , Hang-Ting Lue
发明人： Hsiang-Lan Lung , Hang-Ting Lue
IPC分类号： H01L23/52 , H01L27/102 , H01L27/10 , H01L27/112
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L27/11582
摘要： A 3D memory device is based on an array of electrode pillars and a plurality of electrode planes that intersect the electrode pillars at interface regions that include memory elements that comprise a programmable element and a rectifier. The electrode pillars can be selected using two-dimensional decoding, and the plurality of electrode planes can be selected using decoding on a third dimension.
摘要翻译： 3D存储器件基于电极柱阵列和在包括可编程元件和整流器的存储器元件的界面区域处与电极柱相交的多个电极平面。 可以使用二维解码来选择电极柱，并且可以使用第三维度上的解码来选择多个电极平面。
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公开(公告)号：US08586960B2
公开(公告)日：2013-11-19
申请号：US12142239
申请日：2008-06-19
申请人： Thomas Happ , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
发明人： Thomas Happ , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
IPC分类号： H01L29/06
CPC分类号： H01L27/2481 , G11C13/0004 , G11C2213/72 , H01L27/24 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.
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公开(公告)号：US08471236B2
公开(公告)日：2013-06-25
申请号：US13550091
申请日：2012-07-16
IPC分类号： H01L29/40
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.
摘要翻译： 一种具有平底下电极的相变存储单元及其制造方法。 该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面 导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极 。
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公开(公告)号：US08313979B2
公开(公告)日：2012-11-20
申请号：US13110197
申请日：2011-05-18
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： A device includes a substrate having a first region and a second region. The first region comprises a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal.
摘要翻译： 一种器件包括具有第一区域和第二区域的衬底。 第一区域包括在衬底内具有水平沟道区的第一场效应晶体管，覆盖在水平沟道区上的栅极和覆盖第一场效应晶体管的栅极的第一电介质。 衬底的第二区域包括第二场效应晶体管，其包括延伸穿过第一电介质以接触衬底的第一端子，覆盖第一端子并具有顶表面的第二端子和分离第一和第二端子的垂直沟道区域 。 第二场效应晶体管还包括在第一电介质上并且与垂直沟道区相邻的栅极，栅极具有与第二端子的顶表面共面的顶表面。
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公开(公告)号：US08310864B2
公开(公告)日：2012-11-13
申请号：US12815680
申请日：2010-06-15
IPC分类号： G11C11/00
CPC分类号： H01L27/2454 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148
摘要： A memory device is described that comprises a plurality of bit lines and an array of vertical transistors arranged on the plurality of bit lines. A plurality of word lines is formed along rows of vertical transistors in the array which comprise thin film sidewalls of word line material and arranged so that the thin film sidewalls merge in the row direction, and do not merge in the column direction, to form word lines. The word lines provide “surrounding gate” structures for embodiments in which the vertical transistors are field effect transistors. Memory elements are formed in electrical communication with the vertical transistors. A fully self-aligned process is provided in which the word lines and memory elements are aligned with the vertical transistors without additional patterning steps.
摘要翻译： 描述了包括多个位线和布置在多个位线上的垂直晶体管阵列的存储器件。 多个字线沿阵列中的垂直晶体管行形成，其中包括字线材料的薄膜侧壁，并且布置成使得薄膜侧壁在行方向上合并，并且不在列方向上合并，以形成字 线条。 对于其中垂直晶体管是场效应晶体管的实施例，字线提供周围的栅极结构。 存储元件形成为与垂直晶体管电连通。 提供了完全自对准的工艺，其中字线和存储元件与垂直晶体管对准，而没有额外的图案化步骤。
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公开(公告)号：US08283650B2
公开(公告)日：2012-10-09
申请号：US12550048
申请日：2009-08-28
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.
摘要翻译： 一种具有平底下电极的相变存储单元及其制造方法。 该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面 导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极 。
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公开(公告)号：US08237148B2
公开(公告)日：2012-08-07
申请号：US12792604
申请日：2010-06-02
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： H01L47/00
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C2213/31 , G11C2213/32 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/124 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1691
摘要： Arrays of memory cells are described along with devices thereof and method for manufacturing. Memory cells described herein include self-aligned side wall memory members comprising an active programmable resistive material. In preferred embodiments the area of the memory cell is 4F2, F being the feature size for a lithographic process used to manufacture the memory cell, and more preferably F being equal to a minimum feature size. Arrays of memory cells described herein include memory cells arranged in a cross point array, the array having a plurality of word lines and source lines arranged in parallel in a first direction and having a plurality of bit lines arranged in parallel in a second direction perpendicular to the first direction.
摘要翻译： 描述存储器单元的阵列及其装置及其制造方法。 本文所述的存储单元包括自对准侧壁存储器构件，其包括有源可编程电阻材料。 在优选实施例中，存储单元的面积为4F2，F为用于制造存储单元的光刻工艺的特征尺寸，更优选地，F等于最小特征尺寸。 本文描述的存储器单元的阵列包括布置在交叉点阵列中的存储单元，该阵列具有多个字线和源极线，其沿第一方向平行布置，并且具有沿与第一方向垂直的第二方向平行布置的多个位线 第一个方向。
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10.发明授权Phase change memory cell array with self-converged bottom electrode and method for manufacturing 有权具有自会聚底电极的相变存储单元阵列及其制造方法公开(公告)号：US08178386B2
公开(公告)日：2012-05-15
申请号：US11855983
申请日：2007-09-14
IPC分类号： H01L21/06
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.
摘要翻译： 通过在触点阵列上形成分离层，在分离层上形成图形层并使用光刻工艺在图案形成层中形成掩模开口阵列来制造相变存储器单元的阵列。 通过补偿由平版印刷工艺产生的掩模开口的尺寸变化的过程，在掩模开口内形成蚀刻掩模。 蚀刻掩模用于蚀刻通过分离层以限定暴露下面的触点的电极开口的阵列。 电极材料沉积在电极开口内; 并且存储元件形成在底部电极上。 最后，在存储器元件上形成位线以完成存储器单元。 在所得到的存储器阵列中，底部电极的顶表面的临界尺寸小于掩模开口中存储元件的宽度。
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