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    MEMORY CELL ACCESS DEVICE HAVING A PN-JUNCTION WITH POLYCRYSTALLINE PLUG AND SINGLE-CRYSTAL SEMICONDUCTOR REGIONS
    1.
    发明申请
    MEMORY CELL ACCESS DEVICE HAVING A PN-JUNCTION WITH POLYCRYSTALLINE PLUG AND SINGLE-CRYSTAL SEMICONDUCTOR REGIONS 有权
    具有多晶硅管和单晶半导体区域的PN结的存储器单元访问器件

    公开(公告)号：US20100117049A1

    公开(公告)日：2010-05-13

    申请号：US12267492

    申请日：2008-11-07

    申请人： HSIANG-LAN LUNG ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

    发明人： HSIANG-LAN LUNG ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

    IPC分类号： H01L47/00 ,  H01L21/36

    CPC分类号： H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L29/861 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

    摘要： A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.

    摘要翻译： 存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体插头，第一和第 第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区域形成在单晶半导体中，并且所述第二掺杂半导体区域包括多晶半导体。 此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定第一和第二区域之间的pn结。

    Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions
    4.
    发明授权
    Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions 有权
    具有与多晶硅插头和单晶半导体区域的pn结的存储单元访问装置

    公开(公告)号：US08664689B2

    公开(公告)日：2014-03-04

    申请号：US12267492

    申请日：2008-11-07

    申请人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

    发明人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

    IPC分类号： H01L29/861 ,  H01L29/88

    CPC分类号： H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L29/861 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

    摘要： A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.

    摘要翻译： 存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体插头，第一和第 第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区域形成在单晶半导体中，并且所述第二掺杂半导体区域包括多晶半导体。 此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定第一和第二区域之间的pn结。

    3D two bit-per-cell NAND flash memory
    5.
    发明授权
    3D two bit-per-cell NAND flash memory 有权
    3D双比特单元NAND闪存

    公开(公告)号：US08437192B2

    公开(公告)日：2013-05-07

    申请号：US12785291

    申请日：2010-05-21

    申请人： Hsiang-Lan Lung ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Tien-Yen Wang

    发明人： Hsiang-Lan Lung ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Tien-Yen Wang

    IPC分类号： G11C16/00 ,  G11C16/02 ,  G11C16/04 ,  G11C5/02 ,  G11C5/06

    CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    摘要： A 3D memory device includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.

    摘要翻译： 3D存储器件包括具有垂直NAND串结构的相应阵列的底部和顶部存储立方体。 包括导电材料层的共同源平面位于顶部和底部存储立方体之间。 源平面被提供诸如地的偏置电压，并且选择性地耦合到底部和顶部存储立方体的垂直NAND串结构的一端。 通过源平面与耦合到特定垂直NAND串的另一端的对应位线之间的特定垂直NAND串的电流来读取特定存储器立方体中的存储单元。

    Dielectric charge trapping memory cells with redundancy
    6.
    发明授权
    Dielectric charge trapping memory cells with redundancy 有权
    介质电荷捕获具有冗余的存储单元

    公开(公告)号：US09019771B2

    公开(公告)日：2015-04-28

    申请号：US13661723

    申请日：2012-10-26

    申请人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee

    发明人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee

    IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C16/10

    CPC分类号： G11C16/0475 ,  G11C16/10

    摘要： A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.

    摘要翻译： 介质电荷俘获存储器单元的存储单元阵列和用于对存储在相邻存储器单元中的电荷俘获位置处存储的位的存储单元阵列执行编程，读取和擦除操作的方法。 一些信息存储在第一存储单元中的第一电荷捕获位点和第二相邻存储单元中的第二电荷捕获位点。 在相邻存储器单元中的两个捕获位置处存储电荷增加了存储器单元阵列的数据保留率，因为可以读取每个电荷捕获位点以表示存储在数据站点的数据。 可以独立地并行地读取每个对应的电荷俘获位点，以便比较结果以确定存储在介电电荷俘获存储器单元阵列中的数据位置处的数据值。

    3D memory array arranged for FN tunneling program and erase
    7.
    发明授权
    3D memory array arranged for FN tunneling program and erase 有权
    3D存储阵列用于FN隧道编程和擦除

    公开(公告)号：US08426294B2

    公开(公告)日：2013-04-23

    申请号：US13476964

    申请日：2012-05-21

    申请人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Hang-Ting Lue

    发明人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Hang-Ting Lue

    IPC分类号： H01L29/76

    CPC分类号： G11C16/0458 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11578 ,  H01L27/11582

    摘要： A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

    摘要翻译： 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。

    3D memory array arranged for FN tunneling program and erase
    8.
    发明授权
    3D memory array arranged for FN tunneling program and erase 有权
    3D存储阵列用于FN隧道编程和擦除

    公开(公告)号：US08203187B2

    公开(公告)日：2012-06-19

    申请号：US12705158

    申请日：2010-02-12

    申请人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming Hsiu Lee ,  Hang-Ting Lue

    发明人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming Hsiu Lee ,  Hang-Ting Lue

    IPC分类号： H01L29/76

    CPC分类号： G11C16/0458 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11578 ,  H01L27/11582

    摘要： A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

    摘要翻译： 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。

    3D TWO-BIT-PER-CELL NAND FLASH MEMORY
    9.
    发明申请
    3D TWO-BIT-PER-CELL NAND FLASH MEMORY 有权
    3D双比特单片NAND闪存

    公开(公告)号：US20110286283A1

    公开(公告)日：2011-11-24

    申请号：US12785291

    申请日：2010-05-21

    申请人： HSIANG-LAN LUNG ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming Hsiu Lee ,  Tien-Yen Wang

    发明人： HSIANG-LAN LUNG ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming Hsiu Lee ,  Tien-Yen Wang

    IPC分类号： G11C16/04 ,  H01L21/336

    CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    摘要： A 3D memory device is described which includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.

    摘要翻译： 描述了一种3D存储器件，其包括具有垂直NAND串结构的相应阵列的底部和顶部存储器立方体。 包括导电材料层的共同源平面位于顶部和底部存储立方体之间。 源平面被提供诸如地的偏置电压，并且选择性地耦合到底部和顶部存储立方体的垂直NAND串结构的一端。 通过源平面与耦合到特定垂直NAND串的另一端的对应位线之间的特定垂直NAND串的电流来读取特定存储器立方体中的存储单元。

    3D MEMORY ARRAY ARRANGED FOR FN TUNNELING PROGRAM AND ERASE
    10.
    发明申请
    3D MEMORY ARRAY ARRANGED FOR FN TUNNELING PROGRAM AND ERASE 有权
    3D内存阵列安排FN隧道程序和删除

    公开(公告)号：US20100265773A1

    公开(公告)日：2010-10-21

    申请号：US12705158

    申请日：2010-02-12

    申请人： HSIANG-LAN LUNG ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming Hsiu Lee ,  Hang-Ting Lue

    发明人： HSIANG-LAN LUNG ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming Hsiu Lee ,  Hang-Ting Lue

    IPC分类号： G11C16/04 ,  H01L21/76

    CPC分类号： G11C16/0458 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11578 ,  H01L27/11582

    摘要： A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

    摘要翻译： 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。