利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

97 条记录 (耗时 0.033 秒)

    MEMORY CELL ACCESS DEVICE HAVING A PN-JUNCTION WITH POLYCRYSTALLINE PLUG AND SINGLE-CRYSTAL SEMICONDUCTOR REGIONS
    1.
    发明申请
    MEMORY CELL ACCESS DEVICE HAVING A PN-JUNCTION WITH POLYCRYSTALLINE PLUG AND SINGLE-CRYSTAL SEMICONDUCTOR REGIONS 有权
    具有多晶硅管和单晶半导体区域的PN结的存储器单元访问器件

    公开(公告)号：US20100117049A1

    公开(公告)日：2010-05-13

    申请号：US12267492

    申请日：2008-11-07

    申请人： HSIANG-LAN LUNG ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

    发明人： HSIANG-LAN LUNG ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

    IPC分类号： H01L47/00 ,  H01L21/36

    CPC分类号： H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L29/861 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

    摘要： A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.

    摘要翻译： 存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体插头，第一和第 第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区域形成在单晶半导体中，并且所述第二掺杂半导体区域包括多晶半导体。 此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定第一和第二区域之间的pn结。

    Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions
    4.
    发明授权
    Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions 有权
    具有与多晶硅插头和单晶半导体区域的pn结的存储单元访问装置

    公开(公告)号：US08664689B2

    公开(公告)日：2014-03-04

    申请号：US12267492

    申请日：2008-11-07

    申请人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

    发明人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

    IPC分类号： H01L29/861 ,  H01L29/88

    CPC分类号： H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L29/861 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

    摘要： A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.

    摘要翻译： 存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体插头，第一和第 第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区域形成在单晶半导体中，并且所述第二掺杂半导体区域包括多晶半导体。 此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定第一和第二区域之间的pn结。

    Phase change memory cell and manufacturing method
    5.
    发明授权
    Phase change memory cell and manufacturing method 有权
    相变存储单元及其制造方法

    公开(公告)号：US07688619B2

    公开(公告)日：2010-03-30

    申请号：US11612093

    申请日：2006-12-18

    申请人： Hsiang-Lan Lung ,  Rich Liu ,  Shih-Hung Chen ,  Yi-Chou Chen

    发明人： Hsiang-Lan Lung ,  Rich Liu ,  Shih-Hung Chen ,  Yi-Chou Chen

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/53 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/165 ,  H01L45/1675

    摘要： A phase change memory cell includes first and second electrodes electrically coupled by a phase change element. At least a section of the phase change element comprises a higher reset transition temperature portion and a lower reset transition temperature portion. The lower reset transition temperature portion comprises a phase change region which can be transitioned, by the passage of electrical current therethrough, from generally crystalline to generally amorphous states at a lower temperature than the higher reset transition temperature portion. The phase change element may comprise an outer, generally tubular, higher reset transition temperature portion surrounding an inner, lower reset transition temperature portion.

    摘要翻译： 相变存储单元包括由相变元件电耦合的第一和第二电极。 相变元件的至少一部分包括较高的复位转变温度部分和较低的复位转变温度部分。 下复位转变温度部分包括可以通过电流通过从相对于较高复位转变温度部分的较低温度的大致结晶到大致非晶状态的相变区域。 相变元件可以包括围绕内部，下部复位转变温度部分的外部，大体上管状的较高复位转变温度部分。

    Side wall active pin memory and manufacturing method
    6.
    发明授权
    Side wall active pin memory and manufacturing method 有权
    侧壁有源针存储器及制造方法

    公开(公告)号：US07608503B2

    公开(公告)日：2009-10-27

    申请号：US11285473

    申请日：2005-11-21

    申请人： Hsiang Lan Lung ,  Shih-Hung Chen ,  Yi-Chou Chen

    发明人： Hsiang Lan Lung ,  Shih-Hung Chen ,  Yi-Chou Chen

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/112 ,  G11C2213/52 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/115 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144 ,  H01L45/1691

    摘要： A method of forming a memory cell comprises forming a stack comprising a first electrode, an insulating layer over the first electrode, and a second electrode over the insulating layer, with a side wall on the stack. A side wall spacer comprising a programmable resistive material in electrical communication with the first and second electrodes is formed. The side wall spacer is formed by depositing a layer of programmable resistive material over the side wall of the stack, anisotropically etching the layer of programmable resistive material to remove it in areas away from the side wall, and selectively etching the programmable resistive material according to a pattern to define the width of the side wall spacer. In embodiments described herein, the width is about 40 nanometers or less.

    摘要翻译： 一种形成存储单元的方法包括：在叠层上形成包括第一电极，绝缘层上的绝缘层和绝缘层上的第二电极的堆叠。 形成包括与第一和第二电极电连通的可编程电阻材料的侧壁间隔物。 通过在堆叠的侧壁上沉积可编程电阻材料层来形成侧壁间隔物，各向异性地蚀刻可编程电阻材料层，以便在远离侧壁的区域中去除它，并根据所述方法选择性地蚀刻可编程电阻材料 用于限定侧壁间隔物的宽度的图案。 在本文所述的实施例中，宽度为约40纳米或更小。

    Single-Mask Phase Change Memory Element
    9.
    发明申请
    Single-Mask Phase Change Memory Element 有权
    单掩模相变存储元件

    公开(公告)号：US20070285960A1

    公开(公告)日：2007-12-13

    申请号：US11420107

    申请日：2006-05-24

    申请人： Hsiang-Lan Lung ,  Rich Liu ,  Yi-Chou Chen ,  Shih-Hung Chen

    发明人： Hsiang-Lan Lung ,  Rich Liu ,  Yi-Chou Chen ,  Shih-Hung Chen

    IPC分类号： G11C11/00

    CPC分类号： H01L45/144 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/148 ,  H01L2924/0002 ,  Y10S257/907 ,  H01L2924/00

    摘要： A memory device. An array of memory elements is formed on a semiconductor chip. A parallel array of word lines extends in a first direction, connecting each memory element to a data source, and a parallel array of bit lines extends in a second direction, connecting each memory element to a data source, the second direction forming an acute angle to the first direction. The connection between each bit line and each memory element is a phase change element composed of memory material having at least two solid phases.

    摘要翻译： 一个记忆体装置 存储元件阵列形成在半导体芯片上。 字线的并行阵列沿着第一方向延伸，将每个存储器元件连接到数据源，并行的位线阵列沿第二方向延伸，将每个存储器元件连接到数据源，第二方向形成锐角 到第一个方向。 每个位线与每个存储元件之间的连接是由具有至少两个固相的存储器材料组成的相变元件。

    CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE
    10.
    发明申请
    CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE 有权
    当前的相位变化记忆元素结构

    公开(公告)号：US20100193763A1

    公开(公告)日：2010-08-05

    申请号：US12727672

    申请日：2010-03-19

    申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

    发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

    IPC分类号： H01L45/00

    CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

    摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

    摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝​​缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。