公开(公告)号：US06180419B2

公开(公告)日：2001-01-30

申请号：US08715934

申请日：1996-09-19

申请人： Hsiao-Yi Lin ,  Tan-Fu Lei ,  Ci-Lin Pan ,  Chun Y. Chang ,  Jz-Jan Jeng

发明人： Hsiao-Yi Lin ,  Tan-Fu Lei ,  Ci-Lin Pan ,  Chun Y. Chang ,  Jz-Jan Jeng

IPC分类号： H01L2100

CPC分类号： G01R33/07

摘要： A method for manufacturing a magnetic field transducing device is provided which includes (a) providing a substrate, (b) subjecting the substrate to a semiconductor device fabricating process in order to obtain a magnetic field transducer, (c) forming an oxide over the magnetic field transducer and (d) covering a magnetic film on the oxide in order to obtain the magnetic field transducing device. The semiconductor device fabricating process also includes (b1) utilizing a mask photolithography etching process to form an annular groove on the substrate, (b2) covering a first insulating layer on the substrate and using a second mask photolithography etching process to form a plurality of diffusing openings on the first insulation layer, (b3) forming extrinsic semiconductor region on the substrate exposed by the plurality of diffusing openings, (b4) forming a second insulation layer on the substrate, (b5) utilizing a third mask photolithography etching process to form a plurality of contacts on the extrinsic semiconductor region, and (b6) forming a conductor on the substrate in order to form a connecting line. The magnetic film is preferably made of Ni and Co.

摘要翻译： 提供了一种用于制造磁场换能装置的方法，该方法包括：（a）提供一基板，（b）使基板经受半导体器件制造工艺以获得一磁场换能器;（c） 场传感器和（d）覆盖氧化物上的磁性膜以获得磁场换能装置。 半导体器件制造工艺还包括（b1）利用掩模光刻蚀刻工艺在衬底上形成环形沟槽，（b2）覆盖衬底上的第一绝缘层，并使用第二掩模光刻蚀刻工艺形成多个扩散 在第一绝缘层上的开口，（b3）在由多个扩散开口暴露的衬底上形成非本征半导体区域，（b4）在衬底上形成第二绝缘层，（b5）利用第三掩模光刻蚀刻工艺形成 在外部半导体区域上的多个触点，以及（b6）在基板上形成导体以形成连接线。 磁性膜优选由Ni和Co制成

公开(公告)号：US5565700A

公开(公告)日：1996-10-15

申请号：US426491

申请日：1995-04-20

申请人： Jih W. Chou ,  Joe Ko ,  Chun Y. Chang

发明人： Jih W. Chou ,  Joe Ko ,  Chun Y. Chang

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/7836

摘要： A new surface counter-doped lightly doped source and drain integrated circuit field effect transistor device is described. A gate silicon oxide layer is formed on the silicon substrate. A layer of polysilicon is deposited over the gate silicon oxide layer and etched to form a gate electrode structure. A first ion implantation is performed at a tilt angle to form lightly doped drain regions in the semiconductor substrate wherein the lightly doped drain regions are partially overlapped by the gate electrode structure. A second ion implantation is performed at a larger tilt angle and lower energy than the first ion implantation wherein the second ion implantation counter-dopes the surface of the lightly doped drain regions to form a very lightly doped drain layer thus making the lightly doped drain regions buried regions. A thin layer of silicon oxide is deposited over the surface of the polysilicon gate electrode structure and is anisotropically etched to form ultra thin spacers on the sidewalls of the polysilicon gate electrode structure. A third ion implantation is performed with no tilt angle to complete formation of the lightly doped drain regions. A glasseous layer is deposited over all surfaces of the substrate and flowed followed by metallization and passivation to complete manufacture of the integrated circuit.

摘要翻译： 描述了新的表面反掺杂轻掺杂源极和漏极集成电路场效应晶体管器件。 在硅衬底上形成栅氧化硅层。 一层多晶硅沉积在栅极氧化硅层上并被蚀刻以形成栅电极结构。 以倾斜角度执行第一离子注入，以在半导体衬底中形成轻掺杂漏极区域，其中轻掺杂漏极区域被栅电极结构部分地重叠。 以比第一离子注入更大的倾斜角度和更低的能量执行第二离子注入，其中第二离子注入反掺杂轻掺杂的漏极区的表面以形成非常轻掺杂的漏极层，从而使轻掺杂漏极区 埋葬地区。 氧化硅薄层沉积在多晶硅栅电极结构的表面上，并被各向异性蚀刻以在多晶硅栅电极结构的侧壁上形成超薄间隔物。 执行没有倾斜角的第三离子注入以完成轻掺杂漏极区的形成。 在基板的所有表面上沉积一层胶层，然后流动，随后进行金属化和钝化以完成集成电路的制造。

公开(公告)号：US5308780A

公开(公告)日：1994-05-03

申请号：US94990

申请日：1993-07-22

申请人： Jih W. Chou ,  Joe Ko ,  Chun Y. Chang

发明人： Jih W. Chou ,  Joe Ko ,  Chun Y. Chang

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/7836

摘要： A method of forming an integrated circuit field effect transistor with surface counter-doped lightly doped drain regions is described. A gate silicon oxide layer is formed on the silicon substrate. A layer of polysilicon is deposited over the gate silicon oxide layer and etched to form a gate electrode structure. A first ion implantation is performed at a tilt angle to form lightly doped drain regions in the semiconductor substrate wherein the lightly doped drain regions are partially overlapped by the gate electrode structure. A second ion implantation is performed at a larger tilt angle and lower energy than the first ion implantation wherein the second ion implantation counter-dopes the surface of the lightly doped drain regions to form a very lightly doped drain layer thus making the lightly doped drain regions buried regions. A thin layer of silicon oxide is deposited over the surface of the polysilicon gate electrode structure and is anisotropically etched to form ultra thin spacers on the sidewalls of the polysilicon gate electrode structure. A third ion implantation is performed with no tilt angle to complete formation of the lightly doped drain regions. A glasseous layer is deposited over all surfaces of the substrate and flowed followed by metallization and passivation to complete manufacture of the integrated circuit.

摘要翻译： 描述了一种形成具有表面反掺杂轻掺杂漏极区域的集成电路场效应晶体管的方法。 在硅衬底上形成栅氧化硅层。 一层多晶硅沉积在栅极氧化硅层上并被蚀刻以形成栅电极结构。 以倾斜角度执行第一离子注入，以在半导体衬底中形成轻掺杂漏极区域，其中轻掺杂漏极区域被栅电极结构部分地重叠。 以比第一离子注入更大的倾斜角度和更低的能量执行第二离子注入，其中第二离子注入反掺杂轻掺杂的漏极区的表面以形成非常轻掺杂的漏极层，从而使轻掺杂漏极区 埋葬地区。 氧化硅薄层沉积在多晶硅栅电极结构的表面上，并被各向异性蚀刻以在多晶硅栅电极结构的侧壁上形成超薄间隔物。 执行没有倾斜角的第三离子注入以完成轻掺杂漏极区的形成。 在基板的所有表面上沉积一层胶层，然后流动，随后进行金属化和钝化以完成集成电路的制造。

公开(公告)号：US5354700A

公开(公告)日：1994-10-11

申请号：US96904

申请日：1993-07-26

申请人： Heng-Sheng Huang ,  Chun Y. Chang

发明人： Heng-Sheng Huang ,  Chun Y. Chang

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/265

CPC分类号： H01L29/66742 ,  H01L29/78687 ,  Y10S148/15 ,  Y10S148/16

摘要： An FET thin film transistor is formed with a channel formed of a Si/Si.sub.1-x Ge.sub.x /Si three layer sandwich which serves as the carrier transfer channel. The percentage of germanium is preferably less than 30% and should be less than about 50%. The TFT can be structured as top gate, bottom gate or twin gate structure. The Si/Si.sub.1-x Ge/Si sandwich layer is processed in a continuous process under computer control.

摘要翻译： FET薄膜晶体管形成有由用作载流子传输通道的Si / Si1-xGex / Si三层夹层形成的沟道。 锗的百分比优选小于30％且应小于约50％。 TFT可以被构造为顶栅，底栅或双栅结构。 Si / Si1-xGe / Si夹心层在计算机控制下以连续的方式进行处理。

公开(公告)号：US5469961A

公开(公告)日：1995-11-28

申请号：US290138

申请日：1994-08-15

申请人： Chun Y. Chang

发明人： Chun Y. Chang

IPC分类号： F16K41/12 ,  B65D85/30 ,  B65D85/57

CPC分类号： F16K41/12

摘要： This invention relates to a combined minidisc box, especially a kind of combined minidisc box which can be connected with each other with its left, right, top and bottom sides. The combined minidisc box comprising an upper case and a lower case, wherein the lower case having flanges which can be fitted with grooves of the upper case, two sides of the upper case having respectively a continuous interval dovetails and dovetail slots. Each dovetail and dovetail slots of one side being faced to each dovetail slots and dovetail of the other side, at the top of the upper case having fitting holes and the bottom having fitting posts. The two continuous interval dovetails and dovetail slots of the combined minidisc box can be fitted and connected respectively with continuous interval dovetail slots and dovetails of other combined minidisc boxes. The fitting holes and the fitting posts of the combined minidisc box can furthermore be fitted and connected respectively with fitting posts and fitting holes of other combined minidisc boxes, therefore the combined minidisc box can be connected with each other on its left, right, top and bottom sides.

摘要翻译： 本发明涉及一种组合的迷你盒，特别是一种组合的迷你盒，可以以左，右，上，下两面相互连接。 组合的迷你盒包括上壳体和下壳体，其中下壳体具有可以装配有上壳体的凹槽的凸缘，上壳体的两侧分别具有连续间隔的燕尾榫和燕尾槽。 一侧的每个燕尾和燕尾槽面对每个燕尾槽和另一侧的燕尾榫，在具有装配孔的上壳体的顶部，底部具有配合柱。 组合的迷你盒的两个连续间隔燕尾和燕尾槽可以分别安装和连接其间连续间隔的燕尾槽和其他组合的迷你盒的燕尾。 组合式迷你盒的装配孔和配件柱还可以分别安装和连接其他组合的迷你盒的装配柱和装配孔，因此组合的迷你盒可以在其左，右，上和下相互连接 底部。