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    Method for removal of hard mask used to define noble metal electrode
    1.
    发明授权
    Method for removal of hard mask used to define noble metal electrode 失效
    去除用于定义贵金属电极的硬掩模的方法

    公开(公告)号：US06420272B1

    公开(公告)日：2002-07-16

    申请号：US09460700

    申请日：1999-12-14

    申请人： Hua Shen ,  David Edward Kotecki ,  Satish D. Athavale ,  Jenny Lian ,  Gerhard Kunkel ,  Nimal Chaudhary

    发明人： Hua Shen ,  David Edward Kotecki ,  Satish D. Athavale ,  Jenny Lian ,  Gerhard Kunkel ,  Nimal Chaudhary

    IPC分类号： H01L2100

    CPC分类号： H01L28/60 ,  H01L21/02071 ,  H01L21/31116 ,  H01L21/32139 ,  H01L28/55

    摘要： In semiconductor dynamic random access memory circuits using stacked capacitor storage elements formed using high permittivity dielectric material, it is typical to form the stacked capacitors using noble metal electrodes. Typically, the etching process for the noble metal electrodes requires the use of a hard mask patterning material such as silicon oxide. Removal of this hard mask frequently results in damage to the dielectric surface surrounding the patterned noble metal electrode. A method of removing the hard mask material without damaging the surrounding surface includes the steps of: depositing a soft mask photoresist material over the composite surface, including the hard masked covered noble metal electrode and the dielectric surface, in a manner such that the soft mask material is thinner over the region of the noble metal electrode; removing the portion of the soft mask material over the noble metal electrode leaving the soft mask material over the dielectric surface; etching the hard mask material with the soft mask material protecting the dielectric surface; and removing the remaining portion of the soft mask material.

    摘要翻译： 在使用高介电常数电介质材料形成的叠层电容器存储元件的半导体动态随机存取存储器电路中，典型的是使用贵金属电极形成叠层电容器。 通常，贵金属电极的蚀刻工艺需要使用诸如氧化硅的硬掩模图形材料。 去除这种硬掩模常常导致图案化的贵金属电极周围的电介质表面的损坏。 在不损坏周围表面的情况下去除硬掩模材料的方法包括以下步骤：在复合表面上沉积软掩模光致抗蚀剂材料，包括硬掩蔽的贵金属电极和电介质表面，使得软掩模 材料在贵金属电极的区域上较薄; 在所述贵金属电极上除去所述软掩模材料的所述部分，从而将所述软掩模材料留在所述电介质表面上; 用保护电介质表面的软掩模材料蚀刻硬掩模材料; 以及去除所述软掩模材料的剩余部分。

    Easy to remove hard mask layer for semiconductor device fabrication
    2.
    发明授权
    Easy to remove hard mask layer for semiconductor device fabrication 有权
    易于去除用于半导体器件制造的硬掩模层

    公开(公告)号：US06261967B1

    公开(公告)日：2001-07-17

    申请号：US09501479

    申请日：2000-02-09

    申请人： Satish D. Athavale ,  Hua Shen ,  David Kotecki ,  Jenny Lian

    发明人： Satish D. Athavale ,  Hua Shen ,  David Kotecki ,  Jenny Lian

    IPC分类号： H01L21302

    CPC分类号： H01L21/32136 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/32139 ,  H01L28/55 ,  H01L28/60

    摘要： A method for forming a patterned shape from a noble metal, in accordance with the present invention, includes forming a noble metal layer over a dielectric layer and patterning a hard mask layer on the noble metal layer. The hard mask layer includes a mask material that is selectively removable relative to the noble metal layer and the dielectric layer and capable of withstanding plasma etching. Alternately, the hard mask material may be consumable during the noble metal layer plasma etching. Plasma etching is performed on the noble metal layer in accordance with the patterned hard mask layer. The hard mask layer is removed such that a patterned shape formed in the noble metal layer remains intact after the plasma etching and the hard mask removal.

    摘要翻译： 根据本发明的用于从贵金属形成图案形状的方法包括在电介质层上形成贵金属层并在贵金属层上图形化硬掩模层。 硬掩模层包括可相对于贵金属层和电介质层选择性地移除并能耐受等离子体蚀刻的掩模材料。 或者，在贵金属层等离子体蚀刻期间，硬掩模材料可能是可消耗的。 根据图案化的硬掩模层在贵金属层上进行等离子体蚀刻。 去除硬掩模层，使得在等离子体蚀刻和硬掩模去除之后，在贵金属层中形成的图案形状保持完整。

    Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure
    4.
    发明授权
    Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure 失效
    具有垂直MOSFET和埋地位线导体结构的4F2 STC电池的工艺

    公开(公告)号：US06348374B1

    公开(公告)日：2002-02-19

    申请号：US09597887

    申请日：2000-06-19

    申请人： Satish D. Athavale ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

    发明人： Satish D. Athavale ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

    IPC分类号： H01L218242

    CPC分类号： H01L27/10876 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10885

    摘要： A method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.

    摘要翻译： 一种形成垂直晶体管的方法。 在半导体衬底上形成衬垫层。 通过焊盘层和半导体衬底形成槽。 埋在槽中的位线形成。 位线被电介质材料包围。 形成延伸穿过介电材料的带，以将位线连接到半导体衬底。 槽被填充在位线上方的导体。 导体沿其纵向轴线切割，使得导体保持在槽的一侧。 在半导体衬底之上形成基本上与位线正交的字线槽。 导体的一部分在字线槽下移除，以将导体分离成单独的栅极导体。 字线形成在连接到单独的栅极导体的字线槽中。

    Tungsten hard mask for dry etching aluminum-containing layers
    6.
    发明授权
    Tungsten hard mask for dry etching aluminum-containing layers 失效
    钨硬掩模用于干蚀刻含铝层

    公开(公告)号：US06420099B1

    公开(公告)日：2002-07-16

    申请号：US09366132

    申请日：1999-08-02

    申请人： Martin Gutsche ,  Satish D. Athavale

    发明人： Martin Gutsche ,  Satish D. Athavale

    IPC分类号： G03C500

    CPC分类号： H01L21/32139 ,  H01L21/32136

    摘要： A method for patterning an aluminum-containing layer. A tungsten-containing layer is provided over an aluminum-containing layer. The tungsten-containing layer is patterned to form an opening therein, so that the opening exposes an underlying portion of the aluminum-containing layer. The patterned tungsten-containing layer is exposed to an etch having a substantially higher etch rate of the aluminum-containing layer than of the tungsten-containing layer to remove the exposed portion of the aluminum-containing layer.

    摘要翻译： 一种用于图案化含铝层的方法。 含铝层设置在含铝层上。 将含钨层图案化以在其中形成开口，使得开口暴露含铝层的下面部分。 将图案化的含钨层暴露于具有比含钨层更高的含铝层的蚀刻速率的蚀刻以去除含铝层的暴露部分的蚀刻。

    Method of plasma etching thin films of difficult to dry etch materials
    7.
    发明授权
    Method of plasma etching thin films of difficult to dry etch materials 有权
    等离子体蚀刻难以干蚀刻材料的薄膜的方法

    公开(公告)号：US06548414B2

    公开(公告)日：2003-04-15

    申请号：US09396178

    申请日：1999-09-14

    申请人： Satish D. Athavale ,  Martin Gutsche

    发明人： Satish D. Athavale ,  Martin Gutsche

    IPC分类号： H01L21302

    CPC分类号： H01L28/60 ,  C23F4/00 ,  H01L21/32136

    摘要： A method for etching material which does not readily form volatile compounds in a plasma includes providing a plasma etch chamber including a wafer electrode at an initial temperature. The wafer electrode supports a wafer, and the wafer includes a layer of the material which does not readily form volatile compounds in plasma. The wafer is bombarded with charged particles from a plasma generated in the plasma etch chamber to impart thermal energy to the wafer. A reactive gas flow is provided to react with etch products of the material. Bias power is applied to the wafer electrode to impart bombardment energy to the charged particles incident on the wafer from the plasma such that a predetermined temperature is generated on a surface of the wafer wherein the wafer electrode is maintained at about the initial temperature.

    摘要翻译： 在等离子体中不容易形成挥发性化合物的蚀刻材料的方法包括在初始温度下提供包括晶片电极的等离子体蚀刻室。 晶片电极支撑晶片，并且晶片包括不容易在等离子体中形成挥发性化合物的材料层。 晶圆被等离子体蚀刻室中产生的等离子体的带电粒子轰击，以向晶片赋予热能。 提供反应气流以与材料的蚀刻产物反应。 偏转功率被施加到晶片电极，以从等离子体向入射到晶片上的带电粒子提供轰击能量，从而在晶片的表面上产生预定的温度，其中晶片电极保持在初始温度附近。

    Method and apparatus for minimizing semiconductor wafer arcing during semiconductor wafer processing
    8.
    发明授权
    Method and apparatus for minimizing semiconductor wafer arcing during semiconductor wafer processing 失效
    在半导体晶片处理期间最小化半导体晶片电弧的方法和装置

    公开(公告)号：US06406925B1

    公开(公告)日：2002-06-18

    申请号：US09712707

    申请日：2000-11-14

    申请人： Satish D. Athavale ,  Leslie G. Jerde ,  John A. Meyer

    发明人： Satish D. Athavale ,  Leslie G. Jerde ,  John A. Meyer

    IPC分类号： H01L2166

    CPC分类号： H01L21/6833

    摘要： A method and apparatus for minimizing or eliminating arcing or dielectric breakdown across a wafer during a semiconductor wafer processing step includes controlling the voltage across the wafer so that arcing and/or dielectric breakdown does not occur. Using an electrostatic clamp of the invention and by controlling the specific clamp voltage to within a suitable range of values, the voltage across a wafer is kept below a threshold and thus, arcing and/or dielectric breakdown is reduced or eliminated.

    摘要翻译： 用于在半导体晶片处理步骤期间最小化或消除晶片上的电弧或电介质击穿的方法和装置包括控制晶片两端的电压，使得不发生电弧和/或电介质击穿。 使用本发明的静电夹具并通过将特定钳位电压控制在合适的值范围内，晶片上的电压保持在阈值以下，从而降低或消除了电弧和/或电介质击穿。