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    Structure and method to fabricate MOSFET with short gate
    2.
    发明授权
    Structure and method to fabricate MOSFET with short gate 有权
    用短栅制造MOSFET的结构和方法

    公开(公告)号：US07943467B2

    公开(公告)日：2011-05-17

    申请号：US12016317

    申请日：2008-01-18

    申请人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

    发明人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7833 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S257/901

    摘要： A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.

    摘要翻译： 提供了一种制造半导体器件的方法，其在一个实施例中包括提供包括在衬底顶部的栅极结构的半导体器件，所述栅极结构包括包括上栅极导体和下栅极导体的双栅极导体，其中至少下部 栅极导体包括含硅材料; 去除对下栅极导体选择性的上栅极导体; 在至少所述下栅极导体上沉积金属; 并从金属和下部栅极导体产生硅化物。 在另一个实施例中，本发明的方法包括作为下栅极导体的金属。

    STRUCTURE AND METHOD TO MAKE HIGH PERFORMANCE MOSFET WITH FULLY SILICIDED GATE
    3.
    发明申请
    STRUCTURE AND METHOD TO MAKE HIGH PERFORMANCE MOSFET WITH FULLY SILICIDED GATE 审中-公开
    具有完全硅胶门的高性能MOSFET的结构和方法

    公开(公告)号：US20090236676A1

    公开(公告)日：2009-09-24

    申请号：US12052069

    申请日：2008-03-20

    申请人： Huilong Zhu ,  Daewon Yang ,  Yanfeng Wang ,  Brian J. Greene

    发明人： Huilong Zhu ,  Daewon Yang ,  Yanfeng Wang ,  Brian J. Greene

    IPC分类号： H01L29/78 ,  H01L21/44

    CPC分类号： H01L21/28518 ,  H01L21/28097 ,  H01L21/32155 ,  H01L29/4975 ,  H01L29/66507

    摘要： The present invention in one embodiment provides a method of producing a device including providing a semiconducting device including a gate structure including a silicon containing gate conductor atop a substrate; forming a metal layer on at least the silicon containing gate conductor; and directing chemically inert ions to impact the metal layer, wherein momentum transfer from of the chemically inert ions force metal atoms from the metal layer into the silicon containing gate conductor to provide a silicide gate conductor.

    摘要翻译： 本发明在一个实施例中提供了一种制造器件的方法，该器件包括提供包括栅极结构的半导体器件，该栅极结构包括位于衬底顶部的含硅栅极导体; 在至少含硅栅极导体上形成金属层; 并引导化学惰性离子以冲击金属层，其中来自化学惰性离子的动量传递迫使金属原子从金属层进入含硅栅极导体，以提供硅化物栅极导体。

    STRUCTURE AND METHOD TO FABRICATE MOSFET WITH SHORT GATE
    4.
    发明申请
    STRUCTURE AND METHOD TO FABRICATE MOSFET WITH SHORT GATE 有权
    具有短栅的MOSFET的结构和方法

    公开(公告)号：US20090184378A1

    公开(公告)日：2009-07-23

    申请号：US12016317

    申请日：2008-01-18

    申请人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

    发明人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/7833 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S257/901

    摘要： A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.

    摘要翻译： 提供了一种制造半导体器件的方法，其在一个实施例中包括提供包括在衬底顶部的栅极结构的半导体器件，所述栅极结构包括包括上栅极导体和下栅极导体的双栅极导体，其中至少下部 栅极导体包括含硅材料; 去除对下栅极导体选择性的上栅极导体; 在至少所述下栅极导体上沉积金属; 并从金属和下部栅极导体产生硅化物。 在另一个实施例中，本发明的方法包括作为下栅极导体的金属。

    Hybrid SOI/bulk semiconductor transistors
    6.
    发明授权
    Hybrid SOI/bulk semiconductor transistors 失效
    混合SOI /体半导体晶体管

    公开(公告)号：US07767503B2

    公开(公告)日：2010-08-03

    申请号：US12132853

    申请日：2008-06-04

    申请人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

    发明人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

    IPC分类号： H01L21/84 ,  H01L21/336

    CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

    摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

    摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

    HYBRID SOI/BULK SEMICONDUCTOR TRANSISTORS
    7.
    发明申请
    HYBRID SOI/BULK SEMICONDUCTOR TRANSISTORS 失效
    混合SOI / BULK半导体晶体管

    公开(公告)号：US20080242069A1

    公开(公告)日：2008-10-02

    申请号：US12132853

    申请日：2008-06-04

    申请人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

    发明人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

    摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

    摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

    HYBRID SOI/BULK SEMICONDUCTOR TRANSISTORS
    8.
    发明申请
    HYBRID SOI/BULK SEMICONDUCTOR TRANSISTORS 有权
    混合SOI / BULK半导体晶体管

    公开(公告)号：US20050189589A1

    公开(公告)日：2005-09-01

    申请号：US10708378

    申请日：2004-02-27

    申请人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

    发明人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

    IPC分类号： H01L27/01 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786

    CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

    摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

    摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

    CMOS structures and methods using self-aligned dual stressed layers
    9.
    发明授权
    CMOS structures and methods using self-aligned dual stressed layers 失效
    CMOS结构和方法采用自对准双应力层

    公开(公告)号：US07521307B2

    公开(公告)日：2009-04-21

    申请号：US11380695

    申请日：2006-04-28

    申请人： Huilong Zhu ,  Daewon Yang

    发明人： Huilong Zhu ,  Daewon Yang

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/31116 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/7843

    摘要： A CMOS structure and methods for fabricating the CMOS structure provide that a first stressed layer located over a first transistor and a second stressed layer located over a second transistor abut but do not overlap. Such an abutment absent overlap provides for enhanced manufacturing flexibility when forming a contact to a silicide layer upon a source/drain region within one of the first transistor and the second transistor.

    摘要翻译： 用于制造CMOS结构的CMOS结构和方法提供了位于第一晶体管之上的第一应力层和位于第二晶体管上方的第二应力层邻接但不重叠。 当在第一晶体管和第二晶体管之一内的源极/漏极区域上形成与硅化物层的接触时，这种不存在重叠的基台提供增强的制造灵活性。

    CMOS STRUCTURES AND METHODS FOR IMPROVING YIELD
    10.
    发明申请
    CMOS STRUCTURES AND METHODS FOR IMPROVING YIELD 有权
    CMOS结构和改进方法

    公开(公告)号：US20070252230A1

    公开(公告)日：2007-11-01

    申请号：US11757792

    申请日：2007-06-04

    申请人： Huilong Zhu ,  Daewon Yang

    发明人： Huilong Zhu ,  Daewon Yang

    IPC分类号： H01L21/76 ,  H01L27/12

    CPC分类号： H01L21/31116 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/7843

    摘要： A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress liner (DSL), technology is provided. In order to improve the chip yield, the present invention provides a method in which a sputter etching process is employed to smooth/flatten (i.e., thin) the top surface of the contact etch stopper liners. When DSL technology is used, the inventive sputter etching process is used to reduce the complexity caused by DSL boundaries to smooth/flatten top surface of the DSL, which results in significant yield increase. The present invention also provides a semiconductor structure including at least one etched liner.

    摘要翻译： 提供了使用接触蚀刻阻挡衬垫（包括单中性应力衬垫，单应力衬垫和双应力衬垫（DSL））技术来提高CMOS器件产量的简单，有效和经济的方法。 为了提高芯片产量，本发明提供了一种使用溅射蚀刻工艺来平滑/平坦化（即，薄）接触蚀刻止动衬片的顶表面的方法。 当使用DSL技术时，本发明的溅射蚀刻工艺用于降低由DSL边界引起的DSL平滑/平坦化表面的复杂性，这导致显着的产量增加。 本发明还提供了包括至少一个蚀刻衬里的半导体结构。