摘要:
A CMOS gate electrode formed using a selective growth method and a fabrication method thereof, wherein, in the CMOS gate electrode, a first gate pattern of polysilicon germanium (poly-SiGe) is formed on a PMOS region of a semiconductor substrate, and a second gate pattern of polysilicon is selectively grown from an underlying layer. Although the first gate pattern on the PMOS region is formed of poly-SiGe, the characteristics of the second gate pattern on the NMOS region do not deteriorate, thereby increasing the overall characteristics of a CMOS transistor.
摘要:
Provided is a method for fabricating a semiconductor device. According to the method, an insolating layer which defines an active region on a semiconductor substrate is formed and a gate is formed on the active region of the semiconductor substrate. A first spacer layer which covers the gate and is extended to cover the isolating layer is formed as a first insulating material. A second spacer layer is formed on the first spacer layer as a second insulating material. A second spacer which remains on the sidewalls of the gate by removing some portions of the second spacer layer is formed. A first spacer by a portion of the first spacer layer, which is protected by the second spacer by partially etching the exposed portions of the first spacer layer using the second spacer as a mask so as to reduce the thickness of the first spacer layer, and a protection layer, which protects the insulating layer by remaining the portion of the first spacer of which thickness is reduced, are formed. The second spacer is selectively removed and a gate spacer of the first spacer is formed by removing the remaining protection layer.
摘要:
A semiconductor device having a gate with a negative slope and a method of manufacturing the same. A poly-SiGe layer with a Ge density profile which decreases linearly from the bottom of the gate toward the top of the gate is formed and a poly-SiGe gate having a negative slope is formed by patterning the poly-SiGe layer. It is possible to form a gate whose bottom is shorter than its top defined by photolithography by taking advantage of the variation of etching characteristics with Ge density when patterning. Accordingly, the gate is compact enough for a short channel device and gate resistance can be reduced.
摘要:
CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2
摘要翻译:CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。 绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结,并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小 峰值电平朝向未应变硅活性层的表面。 峰值Ge浓度水平大于x = 0.15,并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。 更优选的是,Si 1-x Ge 2 x层中的Ge的浓度从0.2
摘要:
CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2
摘要翻译:CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。 绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结,并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小 峰值电平朝向未应变硅活性层的表面。 峰值Ge浓度水平大于x = 0.15,并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。 更优选的是,Si 1-x Ge 2 x层中的Ge的浓度从0.2
摘要:
CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2
摘要翻译:CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。 绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结,并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小 峰值电平朝向未应变硅活性层的表面。 峰值Ge浓度水平大于x = 0.15,并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。 更优选的是,Si 1-x Ge 2 x层中的Ge的浓度从0.2
摘要:
CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2
摘要:
CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2
摘要翻译:CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。 绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结,并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小 峰值电平朝向未应变硅活性层的表面。 峰值Ge浓度水平大于x = 0.15,并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。 更优选的是,Si 1-x Ge 2 x层中的Ge的浓度从0.2
摘要:
CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1−xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1−xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peal Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1−xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1−xGex layer varies from the peak level where 0.2
摘要翻译:CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。 绝缘栅电极也设置在未应变硅有源层的表面上。 还可以在电绝缘层和未应变硅活性层之间设置Si 1-x SB> Ge x SB> 层。 Si 1-x SB> Ge x SB> 层与未应变硅活性层形成第一结,并具有梯度浓度 Ge在从峰值电平向未应变硅有源层的表面延伸的第一方向上单调减小。 Peal Ge浓度水平大于x = 0.15,并且Si 1-x SB> Ge x SB> 层在峰值电平变化到在第一结处小于约x = 0.1的电平。 Ge在第一结处的浓度可能是突然的。 更优选的是,Si > u> b> u>
层中的Ge的浓度, x <0.4到第一结处x = 0的水平。 相对于表面,Si 1-x SB> Ge x SB> 层也具有退化的砷掺杂特性。 >
摘要:
Provided are a metal oxide semiconductor (MOS) transistor and a complementary MOS (CMOS) transistor each having a strained channel epi layer, and methods of fabricating the transistors. The MOS transistor may include at least one active region defined by an isolation structure formed in a substrate. At least one channel trench may be formed in a part of the at least one active region. At least one strained channel epi layer may be in the at least one channel trench. At least one gate electrode may be aligned on the at least one strained channel epi layer. Sources/drains may be arranged in the at least one active region along both sides of the at least one strained channel epi layer.