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    Digital proportional integral loop filter
    4.
    发明授权
    Digital proportional integral loop filter 有权
    数字比例积分环路滤波器

    公开(公告)号：US07961038B2

    公开(公告)日：2011-06-14

    申请号：US12631637

    申请日：2009-12-04

    申请人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

    发明人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

    IPC分类号： H03B1/00

    CPC分类号： G05B1/03

    摘要： A digital proportional integral loop filter is provided. A first proportional amplification unit multiplies a phase error value by a first proportional loop gain, and a first integral amplification unit multiplies a phase error accumulation value by a first integral loop gain. A second proportional amplification unit multiplies the phase error value by a second proportional loop gain, and a second integral amplification unit multiplies the phase error accumulation value by a second integral loop gain. A first offset value generation unit generates a first offset value by subtracting the second proportional loop gain from the first proportional loop gain and multiplying a resulting value by a phase error average value, and a second offset value generation unit generates a second offset value by subtracting the second integral loop gain from the first integral loop gain and multiplying a resulting value by a phase error accumulation average value.

    摘要翻译： 提供了数字比例积分环路滤波器。 第一比例放大单元将相位误差值乘以第一比例环路增益，并且第一积分放大单元将相位误差累积值乘以第一积分环路增益。 第二比例放大单元将相位误差值乘以第二比例环路增益，第二积分放大单元将相位误差累积值乘以第二积分环路增益。 第一偏移值生成单元通过从第一比例环增益中减去第二比例环增益并将结果值乘以相位误差平均值来生成第一偏移值，第二偏移值生成单元通过减去第二偏移值生成单位生成第二偏移值 来自第一积分环路增益的第二积分环路增益，并将得到的值乘以相位误差累积平均值。

    TIME-TO-DIGITAL CONVERTER AND ALL DIGITAL PHASE-LOCKED LOOP INCLUDING THE SAME
    5.
    发明申请
    TIME-TO-DIGITAL CONVERTER AND ALL DIGITAL PHASE-LOCKED LOOP INCLUDING THE SAME 有权
    时数转换器和所有数字相位锁定环路

    公开(公告)号：US20110148490A1

    公开(公告)日：2011-06-23

    申请号：US12956498

    申请日：2010-11-30

    申请人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

    发明人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

    IPC分类号： H03L7/08 ,  H03M1/50

    CPC分类号： H03L7/095 ,  G04F10/005 ,  H03L7/085 ,  H03L7/103 ,  H03L2207/50

    摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

    摘要翻译： 全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出来改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

    Time-to-digital converter and all digital phase-locked loop including the same
    6.
    发明授权
    Time-to-digital converter and all digital phase-locked loop including the same 有权
    时间到数字转换器和所有数字锁相环包括相同的

    公开(公告)号：US08344772B2

    公开(公告)日：2013-01-01

    申请号：US12956498

    申请日：2010-11-30

    申请人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

    发明人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

    IPC分类号： H03L7/06

    CPC分类号： H03L7/095 ,  G04F10/005 ,  H03L7/085 ,  H03L7/103 ,  H03L2207/50

    摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

    摘要翻译： 全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

    Apparatus for compensating for error of time-to-digital converter
    7.
    发明授权
    Apparatus for compensating for error of time-to-digital converter 有权
    用于补偿时间 - 数字转换器误差的装置

    公开(公告)号：US07999707B2

    公开(公告)日：2011-08-16

    申请号：US12629020

    申请日：2009-12-01

    申请人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

    发明人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

    IPC分类号： H03M1/06

    CPC分类号： G04F10/06 ,  H03L7/085 ,  H03L2207/50

    摘要： An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors.

    摘要翻译： 公开了用于补偿时间 - 数字转换器（TDC）的误差的装置，以从包括TDC的相位检测器和包括TDC误差的相位误差接收延迟相位并补偿TDC误差以具有时间 分辨率提高N倍（N是自然数）。 该装置包括：分段和乘法单元，将延迟相位分片N次（N是自然数），以产生第一至第（N-1）个分段延迟相位; 加法单元将第一到第（N-1）个分段延迟相位中的每一个相加到相位误差，以产生第一到第（N-1）个相位误差; 以及比较单元从相位误差和第一到第（N-1）个相位误差获取最接近实际相位误差的相位误差补偿值。

    APPARATUS FOR COMPENSATING FOR ERROR OF TIME-TO-DIGITAL CONVERTER
    8.
    发明申请
    APPARATUS FOR COMPENSATING FOR ERROR OF TIME-TO-DIGITAL CONVERTER 有权
    用于补偿时间到数字转换器错误的装置

    公开(公告)号：US20100134335A1

    公开(公告)日：2010-06-03

    申请号：US12629020

    申请日：2009-12-01

    申请人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

    发明人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

    IPC分类号： H03M1/06

    CPC分类号： G04F10/06 ,  H03L7/085 ,  H03L2207/50

    摘要： An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors.

    摘要翻译： 公开了用于补偿时间 - 数字转换器（TDC）的误差的装置，以从包括TDC的相位检测器和包括TDC误差的相位误差接收延迟相位并补偿TDC误差以具有时间 分辨率提高N倍（N是自然数）。 该装置包括：分段和乘法单元，将延迟相位分片N次（N是自然数），以产生第一到第（N-1）个分段延迟相位; 加法单元将第一到第（N-1）个分段延迟相位中的每一个相加到相位误差，以产生第一到第（N-1）个相位误差; 以及比较单元从相位误差和第一到第（N-1）个相位误差获取最接近实际相位误差的相位误差补偿值。