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公开(公告)号:US20100080044A1
公开(公告)日:2010-04-01
申请号:US12570159
申请日:2009-09-30
申请人: Hyeoung-won SEO , Young-yong BYUN , Seong-jin JANG , Sang-woong SHIN , Soo-ho SHIN , Won-woo LEE , Jeong-soo PARK
发明人: Hyeoung-won SEO , Young-yong BYUN , Seong-jin JANG , Sang-woong SHIN , Soo-ho SHIN , Won-woo LEE , Jeong-soo PARK
CPC分类号: G11C8/14 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C2207/005
摘要: According to some of the inventive concepts, a semiconductor memory device may include a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.
摘要翻译: 根据一些本发明的概念,半导体存储器件可以包括多个存储单元块,其包括具有位线的第一存储器单元块,边沿读出放大器块,包括耦合到第一位的位线的一部分的边沿读出放大器 存储单元块和耦合到边缘读出放大器的平衡电容单元。