公开(公告)号：US20100210104A1

公开(公告)日：2010-08-19

申请号：US12427870

申请日：2009-04-22

申请人： Hyung Soon Park ,  Noh Jung Kwak ,  Seung Jin Yeom ,  Choon Kun Ryu ,  Jong Goo Jung ,  Sung Jun Kim

发明人： Hyung Soon Park ,  Noh Jung Kwak ,  Seung Jin Yeom ,  Choon Kun Ryu ,  Jong Goo Jung ,  Sung Jun Kim

IPC分类号： H01L21/768 ,  H01L21/306

CPC分类号： H01L21/02074 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76883

摘要： A process for forming a copper wiring and the prevention of copper ion migration in a semiconductor device is disclosed herein. The process includes conducting a post-cleaning process for a copper layer that is to form the cooper wiring after already having undergone a CMP process. The post-cleaning process includes conducting a primary chemical cleaning using a citric acid-based chemical. A secondary chemical cleaning is then conducted on the copper layer having undergone the primary chemical cleaning using an ascorbic acid-based chemical. After the post-cleaning process is completed, the migration of copper ions over time is prevented thereby improving the reliability of the semiconductor device.

摘要翻译： 本文公开了一种用于形成铜布线的方法和防止半导体器件中的铜离子迁移。 该方法包括对经过CMP工艺形成铜线的铜层进行后清洗处理。 后清洗过程包括使用基于柠檬酸的化学品进行初级化学清洗。 然后在使用抗坏血酸的化学品进行了主要化学清洗的铜层上进行二次化学清洗。 在完成后清洗处理之后，防止了铜离子随时间的迁移，从而提高了半导体器件的可靠性。

公开(公告)号：US08252686B2

公开(公告)日：2012-08-28

申请号：US12427870

申请日：2009-04-22

申请人： Hyung Soon Park ,  Noh Jung Kwak ,  Seung Jin Yeom ,  Choon Kun Ryu ,  Jong Goo Jung ,  Sung Jun Kim

发明人： Hyung Soon Park ,  Noh Jung Kwak ,  Seung Jin Yeom ,  Choon Kun Ryu ,  Jong Goo Jung ,  Sung Jun Kim

IPC分类号： H01L21/302

CPC分类号： H01L21/02074 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76883

摘要： A process for forming a copper wiring and the prevention of copper ion migration in a semiconductor device is disclosed herein. The process includes conducting a post-cleaning process for a copper layer that is to form the cooper wiring after already having undergone a CMP process. The post-cleaning process includes conducting a primary chemical cleaning using a citric acid-based chemical. A secondary chemical cleaning is then conducted on the copper layer having undergone the primary chemical cleaning using an ascorbic acid-based chemical. After the post-cleaning process is completed, the migration of copper ions over time is prevented thereby improving the reliability of the semiconductor device.

摘要翻译： 本文公开了一种用于形成铜布线的方法和防止半导体器件中的铜离子迁移。 该方法包括在已经经过CMP工艺的铜层之后对铜层进行后清洗处理。 后清洗过程包括使用基于柠檬酸的化学品进行初级化学清洗。 然后在使用抗坏血酸的化学品进行了主要化学清洗的铜层上进行二次化学清洗。 在完成后清洗处理之后，防止了铜离子随时间的迁移，从而提高了半导体器件的可靠性。

公开(公告)号：US5908672A

公开(公告)日：1999-06-01

申请号：US950923

申请日：1997-10-15

申请人： Choon Kun Ryu ,  Judy H. Huang ,  David Cheung

发明人： Choon Kun Ryu ,  Judy H. Huang ,  David Cheung

IPC分类号： C23C16/34 ,  C23C16/40 ,  H01L21/3105 ,  H01L21/316

CPC分类号： H01L21/02131 ,  C23C16/345 ,  C23C16/401 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/31051 ,  H01L21/31629 ,  Y10S438/958

摘要： A planarized passivation layer is described. A planarized passivation layer of the present invention preferably includes a fluorosilicate glass (FSG) layer and a silicon nitride layer. The FSG layer is preferably deposited using triethoxyfluorosilane (TEFS) and tetraethoxyorthosilicate (TEOS). The inclusion of fluorine in the process chemistry provides good gap-fill characteristics in the film thus formed. The TEFS-based process employed by the present invention employs a low deposition rate, on the order of less than about 4500 .ANG./min, and preferably above 3000 .ANG./min, when depositing the FSG layer. The use of low deposition rate results in a positively sloped profile, preventing the formation of voids during the deposition of the FSG layer and the silicon nitride layer.

摘要翻译： 描述了平坦化的钝化层。 本发明的平坦化钝化层优选包括氟硅酸盐玻璃（FSG）层和氮化硅层。 FSG层优选使用三乙氧基氟硅烷（TEFS）和原硅酸四乙酯（TEOS）沉积。 在工艺化学中包含氟在由此形成的膜中提供良好的间隙填充特性。 当沉积FSG层时，本发明采用的基于TEFS的方法使用低沉积速率，小于约4500安培/分钟，优选高于3000安培/分钟。 使用低沉积速率导致正倾斜的轮廓，防止在沉积FSG层和氮化硅层期间形成空隙。

公开(公告)号：US07205242B2

公开(公告)日：2007-04-17

申请号：US10880278

申请日：2004-06-29

申请人： Choon Kun Ryu

发明人： Choon Kun Ryu

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L27/115 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76224 ,  H01L27/11521

摘要： The present invention relates to a method for forming an insulating layer in a semiconductor device. After a first oxide film is formed in a trench, an impurity remaining on the first oxide film in the process of etching the first oxide film using a gas containing fluorine is stripped using oxygen plasma or hydrogen plasma. Thus, it can prevent degradation of device properties due to diffusion of the impurity without additional equipment. Therefore, it can help improve reliability of a next-generation device.

摘要翻译： 本发明涉及一种在半导体器件中形成绝缘层的方法。 在沟槽中形成第一氧化物膜之后，使用氧等离子体或氢等离子体来剥离在使用含氟气体蚀刻第一氧化膜的过程中残留在第一氧化物膜上的杂质。 因此，它可以防止由于杂质扩散而导致的器件性质的劣化，而没有附加的设备。 因此，它可以帮助提高下一代设备的可靠性。

公开(公告)号：US09406871B2

公开(公告)日：2016-08-02

申请号：US14807267

申请日：2015-07-23

申请人： Masahiko Nakayama ,  Masatoshi Yoshikawa ,  Tadashi Kai ,  Yutaka Hashimoto ,  Masaru Toko ,  Hiroaki Yoda ,  Jae Geun Oh ,  Keum Bum Lee ,  Choon Kun Ryu ,  Hyung Suk Lee ,  Sook Joo Kim

发明人： Masahiko Nakayama ,  Masatoshi Yoshikawa ,  Tadashi Kai ,  Yutaka Hashimoto ,  Masaru Toko ,  Hiroaki Yoda ,  Jae Geun Oh ,  Keum Bum Lee ,  Choon Kun Ryu ,  Hyung Suk Lee ,  Sook Joo Kim

IPC分类号： H01L43/00 ,  H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10

CPC分类号： H01L43/02 ,  H01L27/222 ,  H01L27/224 ,  H01L27/226 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

摘要： According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.

公开(公告)号：US06737349B2

公开(公告)日：2004-05-18

申请号：US10310722

申请日：2002-12-05

申请人： Choon Kun Ryu

发明人： Choon Kun Ryu

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/76826

摘要： A method of forming a copper wiring in a semiconductor device. The method can prevent an increase of a dielectric constant of a low dielectric constant film and making bad deposition of a copper anti-diffusion film, due to infiltration of an organic solvent, an etch gas, etc. into the low dielectric constant film exposed at the side of a damascene pattern during a wet cleaning process for removing polymer generating when a portion of the low dielectric constant film is etched to form the damascene pattern or during a photoresist pattern strip process. In order accomplish these purpose, a CFXHY polymer layer is changed to a SiCH film using SiH4 plasma without removing the polymer layer formed at the side of the damascene pattern. Therefore, infiltration of an organic solvent or an etch gas can be prevented due to the SiCH film having a condensed film quality and a good mechanical strength. Also, the SiCH film serves as a copper anti-diffusion film and in structure, supports a porous low dielectric constant film having a weak mechanical strength.

摘要翻译： 一种在半导体器件中形成铜布线的方法。 该方法可以防止由于有机溶剂，蚀刻气体等渗透到暴露于低介电常数膜的低介电常数薄膜中而导致的低介电常数膜的介电常数的增加和铜防扩散膜的沉积不良 在低温介电常数膜的一部分被蚀刻以形成镶嵌图案或者在光致抗蚀剂图案剥离处理期间，在湿式清洗过程中除去聚合物产生的镶嵌图案的一侧。 为了达到这些目的，使用SiH 4等离子体将CFXHY聚合物层改变为SiCH膜，而不除去在镶嵌图案侧形成的聚合物层。 因此，由于具有冷凝膜质量和良好机械强度的SiCH膜，可以防止有机溶剂或蚀刻气体的渗透。 此外，SiCH膜用作铜抗扩散膜，并且在结构上支持机械强度低的多孔低介电常数膜。

公开(公告)号：US09385304B2

公开(公告)日：2016-07-05

申请号：US14203249

申请日：2014-03-10

申请人： Masahiko Nakayama ,  Tadashi Kai ,  Masaru Toko ,  Hiroaki Yoda ,  Hyung Suk Lee ,  Jae Geun Oh ,  Choon Kun Ryu ,  Min Suk Lee

发明人： Masahiko Nakayama ,  Tadashi Kai ,  Masaru Toko ,  Hiroaki Yoda ,  Hyung Suk Lee ,  Jae Geun Oh ,  Choon Kun Ryu ,  Min Suk Lee

IPC分类号： H01L27/00 ,  H01L43/02 ,  H01L43/12 ,  H01L45/00 ,  G11C11/56 ,  G11C11/15 ,  G11C11/16 ,  H01L27/22 ,  H01L27/24 ,  H01L43/08 ,  H01L43/10

CPC分类号： H01L43/02 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/5607 ,  H01L27/222 ,  H01L27/228 ,  H01L27/2463 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/04

摘要： According to one embodiment, a magnetic memory is disclosed. The memory includes a conductive layer containing a first metal material, a stacked body above the conductive layer, and including a first magnetization film containing a second metal material, a second magnetization film, and a tunnel barrier layer between the first magnetization film and the second magnetization film, and an insulating layer on a side face of the stacked body, and containing an oxide of the first metal material. The first magnetization film and/or the second magnetization film includes a first region positioned in a central portion, and a second region positioned in an edge portion and containing As, P, Ge, Ga, Sb, In, N, Ar, He, F, Cl, Br, I, Si, B, C, O, Zr, Tb, S, Se, or Ti.

摘要翻译： 根据一个实施例，公开了一种磁存储器。 该存储器包括一个包含第一金属材料的导电层，在该导电层上方的层叠体，并且包括一个第一磁化膜，该第一磁化膜含有第二金属材料，第二磁化膜和第一磁化膜与第二磁化膜之间的隧道势垒层 磁化膜和层叠体的侧面上的绝缘层，并且含有第一金属材料的氧化物。 第一磁化膜和/或第二磁化膜包括位于中心部分的第一区域和位于边缘部分中并且包含As，P，Ge，Ga，Sb，In，N，Ar，He的第二区域， F，Cl，Br，I，Si，B，C，O，Zr，Tb，S，Se或Ti。

公开(公告)号：US09123879B2

公开(公告)日：2015-09-01

申请号：US14202802

申请日：2014-03-10

申请人： Masahiko Nakayama ,  Masatoshi Yoshikawa ,  Tadashi Kai ,  Yutaka Hashimoto ,  Masaru Toko ,  Hiroaki Yoda ,  Jae Geun Oh ,  Keum Bum Lee ,  Choon Kun Ryu ,  Hyung Suk Lee ,  Sook Joo Kim

发明人： Masahiko Nakayama ,  Masatoshi Yoshikawa ,  Tadashi Kai ,  Yutaka Hashimoto ,  Masaru Toko ,  Hiroaki Yoda ,  Jae Geun Oh ,  Keum Bum Lee ,  Choon Kun Ryu ,  Hyung Suk Lee ,  Sook Joo Kim

IPC分类号： H01L27/00 ,  H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

CPC分类号： H01L43/02 ,  H01L27/222 ,  H01L27/224 ,  H01L27/226 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

摘要： According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.

摘要翻译： 根据一个实施例，公开了一种磁阻元件。 磁阻元件包括参考层，隧道势垒层，存储层。 存储层包括第一区域和设置在第一区域外部以围绕第一区域的第二区域，第二区域包括包含在第一区域中的元素，而另一个元素不同于元件。 磁阻元件进一步包括盖层，该盖层包括第三区域和设置在第三区域外部以包围第三区域的第四区域，第四区域包括包括在第三区域中的元件和另一元件。

公开(公告)号：US07211524B2

公开(公告)日：2007-05-01

申请号：US10310143

申请日：2002-12-05

申请人： Choon Kun Ryu ,  Tae Kyung Kim

发明人： Choon Kun Ryu ,  Tae Kyung Kim

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02126 ,  C23C16/401 ,  C23C16/515 ,  C23C16/56 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31633 ,  H01L21/31695

摘要： The present invention relates to a method of forming an insulating film in a semiconductor device. After a mixed gas of alkyl silane gas and N2O gas is supplied into the deposition equipment, a radio frequency power including a short pulse wave for causing incomplete reaction upon a gas phase reaction is applied to generate nano particle. The nano particle is then reacted to oxygen radical to form the insulating film including a plurality of nano voids. A low-dielectric insulating film that can be applied to the nano technology even in the existing LECVD equipment is formed.

摘要翻译： 本发明涉及在半导体器件中形成绝缘膜的方法。 在沉积设备中提供烷基硅烷气体和N 2 O 2气体的混合气体后，施加包括在气相反应中引起不完全反应的短脉冲波的射频功率以产生纳米 粒子。 然后使纳米颗粒与氧自由基反应以形成包括多个纳米空隙的绝缘膜。 形成即使在现有的LECVD设备中也可应用于纳米技术的低介电绝缘膜。

公开(公告)号：US5990000A

公开(公告)日：1999-11-23

申请号：US803304

申请日：1997-02-20

申请人： Soonil Hong ,  Choon Kun Ryu ,  Michael P. Nault ,  Kaushal K. Singh ,  Anthony Lam ,  Virendra V. S. Rana ,  Andrew Conners

发明人： Soonil Hong ,  Choon Kun Ryu ,  Michael P. Nault ,  Kaushal K. Singh ,  Anthony Lam ,  Virendra V. S. Rana ,  Andrew Conners

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/306

CPC分类号： H01L21/31051

摘要： A method and an apparatus for depositing a dielectric layer to fill in a gap between adjacent metal lines. In preferred embodiments of the method, a first dielectric layer is deposited over the lines and subsequently etched using both chemical and physical etchback steps. After the etchback steps are completed, a second dielectric layer is deposited over the first dielectric layer to fill in the gap.

摘要翻译： 一种用于沉积介电层以填充相邻金属线之间的间隙的方法和装置。 在该方法的优选实施例中，第一电介质层沉积在线上并随后使用化学和物理回蚀步骤进行蚀刻。 在回蚀步骤完成之后，第二介电层沉积在第一介电层上以填充间隙。