公开(公告)号：US10566424B2

公开(公告)日：2020-02-18

申请号：US15820770

申请日：2017-11-22

Applicant: Infineon Technologies AG

Inventor： Nico Caspary ,  Helmut Oefner ,  Hans-Joachim Schulze

IPC: H01L29/10 ,  H01L29/167 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  C30B15/04 ,  C30B29/06 ,  C30B30/04

Abstract: A method of manufacturing a silicon wafer is provided that includes extracting an n-type silicon ingot over an extraction time period from the a silicon melt comprising n-type dopants; adding p-type dopants to the silicon melt over at least part of the extraction time period, thereby compensating an n-type doping in the n-type silicon ingot by 10% to 80%; slicing the silicon ingot; forming hydrogen related donors in the silicon wafer by irradiating the silicon wafer with protons; and annealing the silicon wafer subsequent to the forming of the hydrogen related donors in the silicon wafer.

公开(公告)号：US09786748B2

公开(公告)日：2017-10-10

申请号：US14722591

申请日：2015-05-27

Applicant: Infineon Technologies AG

Inventor： Nico Caspary ,  Hans-Joachim Schulze

IPC: H01L29/15 ,  H01L29/36 ,  C30B15/00 ,  C30B29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/167 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861

CPC classification number: H01L29/36 ,  C30B15/00 ,  C30B15/04 ,  C30B15/20 ,  C30B29/06 ,  C30B33/00 ,  H01L29/0878 ,  H01L29/16 ,  H01L29/167 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/8611

Abstract: A CZ silicon ingot is doped with donors and acceptors and includes an axial gradient of doping concentration of the donors and of the acceptors. An electrically active net doping concentration, which is based on a difference between the doping concentrations of the donors and acceptors varies by less than 60% for at least 40% of an axial length of the CZ silicon ingot due to partial compensation of at least 20% of the doping concentration of the donors by the acceptors.

公开(公告)号：US10014400B2

公开(公告)日：2018-07-03

申请号：US15650504

申请日：2017-07-14

Applicant: Infineon Technologies AG

Inventor： Helmut Oefner ,  Nico Caspary ,  Mohammad Momeni ,  Reinhard Ploss ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze

IPC: H01L29/739 ,  H01L21/02 ,  H01L29/66 ,  H01L21/324 ,  H01L21/268 ,  H01L29/10 ,  H01L21/18 ,  H01L21/322 ,  H01L21/28 ,  H01L21/225

CPC classification number: H01L29/7393 ,  H01L21/02002 ,  H01L21/02005 ,  H01L21/02008 ,  H01L21/0201 ,  H01L21/02016 ,  H01L21/187 ,  H01L21/2257 ,  H01L21/268 ,  H01L21/28238 ,  H01L21/3221 ,  H01L21/3225 ,  H01L21/324 ,  H01L21/3242 ,  H01L21/76256 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66325 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

Abstract: A semiconductor device includes: a semiconductor substrate having a first side, a second side opposite the first side, and a thickness; at least one semiconductor component integrated in the semiconductor substrate; a first metallization at the first side of the semiconductor substrate; and a second metallization at the second side of the semiconductor substrate. The semiconductor substrate has an oxygen concentration along a thickness line of the semiconductor substrate which has a global maximum at a position of 20% to 80% of the thickness relative to the first side. The global maximum is at least 2-times larger than the oxygen concentrations at each of the first side and the second side of the semiconductor substrate.

公开(公告)号：US20160305040A1

公开(公告)日：2016-10-20

申请号：US15189067

申请日：2016-06-22

Applicant: Infineon Technologies AG

Inventor： Nico Caspary ,  Hans-Joachim Schulze

IPC: C30B15/04 ,  H01L29/16 ,  C30B15/20 ,  C30B29/06 ,  C30B33/00 ,  H01L29/36 ,  H01L29/739

CPC classification number: H01L29/36 ,  C30B15/00 ,  C30B15/04 ,  C30B15/20 ,  C30B29/06 ,  C30B33/00 ,  H01L29/0878 ,  H01L29/16 ,  H01L29/167 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/8611

Abstract: A method of manufacturing a silicon wafer includes extracting an n-type silicon ingot over an extraction time period from a silicon melt comprising n-type dopants, adding p-type dopants to the silicon melt over at least part of the extraction time period, so as to compensate an n-type doping in the n-type silicon ingot by 20% to 80%, and slicing the silicon ingot.

Abstract translation: 一种制造硅晶片的方法包括：从包括n型掺杂剂的硅熔体在提取时间段内提取n型硅锭，在至少部分提取时间段内向硅熔体中加入p型掺杂剂，因此 以补偿n型硅锭中的n型掺杂20％至80％，并切割硅锭。

公开(公告)号：US10337117B2

公开(公告)日：2019-07-02

申请号：US14535416

申请日：2014-11-07

Applicant: Infineon Technologies AG

Inventor： Nico Caspary ,  Hans-Joachim Schulze

IPC: C01B33/00 ,  C30B15/04 ,  C30B29/06 ,  C01B33/02

Abstract: A method of Czochralski growth of a silicon ingot includes melting a mixture of silicon material and an n-type dopant material in a crucible. The silicon ingot is extracted from the molten silicon during an extraction time period. The silicon ingot is doped with additional n-type dopant material during at least one sub-period of the extraction time period.

公开(公告)号：US09728395B2

公开(公告)日：2017-08-08

申请号：US14867839

申请日：2015-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Helmut Oefner ,  Nico Caspary ,  Mohammad Momeni ,  Reinhard Ploss ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze

IPC: H01L21/02 ,  H01L21/268 ,  H01L21/324 ,  H01L29/66 ,  H01L21/18 ,  H01L21/225 ,  H01L21/28 ,  H01L21/322

CPC classification number: H01L29/7393 ,  H01L21/02002 ,  H01L21/02005 ,  H01L21/02008 ,  H01L21/0201 ,  H01L21/02016 ,  H01L21/187 ,  H01L21/2257 ,  H01L21/268 ,  H01L21/28238 ,  H01L21/3221 ,  H01L21/3225 ,  H01L21/324 ,  H01L21/3242 ,  H01L21/76256 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66325 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

Abstract: A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.

公开(公告)号：US20160104622A1

公开(公告)日：2016-04-14

申请号：US14867839

申请日：2015-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Helmut Oefner ,  Nico Caspary ,  Mohammad Momeni ,  Reinhard Ploss ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze

IPC: H01L21/28 ,  H01L21/322

CPC classification number: H01L29/7393 ,  H01L21/02002 ,  H01L21/02005 ,  H01L21/02008 ,  H01L21/0201 ,  H01L21/02016 ,  H01L21/187 ,  H01L21/2257 ,  H01L21/268 ,  H01L21/28238 ,  H01L21/3221 ,  H01L21/3225 ,  H01L21/324 ,  H01L21/3242 ,  H01L21/76256 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66325 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

Abstract: A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.

Abstract translation: 一种用于制造衬底晶片100的方法包括提供具有第一侧面（111）和第二侧面（112）的器件晶片（110）; 至少在第二侧（112）的区域（112a）中对器件晶片（110）进行第一高温工艺以减少器件晶片（110）的氧含量; 将器件晶片（110）的第二侧（112）接合到载体晶片（120）的第一侧（121）以形成衬底晶片（100）; 处理衬底晶片（100）的第一侧（101）以减小器件晶片（110）的厚度; 对所述衬底晶片（100）进行第二高温处理以至少减少所述器件晶片（110）的氧含量; 以及在所述第二高温处理之后至少部分地将至少一个半导体部件（140）集成到所述器件晶片（110）中。

公开(公告)号：US11242616B2

公开(公告)日：2022-02-08

申请号：US15953093

申请日：2018-04-13

Applicant: Infineon Technologies AG

Inventor： Nico Caspary ,  Hans-Joachim Schulze

IPC: C01B33/02 ,  C30B15/04 ,  C30B29/06

Abstract: A silicon ingot has opposite ends. A specific resistance, measured along an axis between the opposite ends of the silicon ingot, has at least one point of inflection where a concavity of the specific resistance changes along the axis. According to another embodiment, a silicon ingot has a first ingot part and a second ingot part between opposite ends of the silicon ingot. The first ingot part has a different specific resistance than the second ingot part. In a region of the silicon ingot between the first and second ingot parts, the specific resistance has at least one point of inflection where a concavity of the specific resistance changes.

公开(公告)号：US10957767B2

公开(公告)日：2021-03-23

申请号：US16773225

申请日：2020-01-27

Applicant: Infineon Technologies AG

Inventor： Nico Caspary ,  Helmut Oefner ,  Hans-Joachim Schulze

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/739 ,  H01L29/36 ,  C30B15/04 ,  C30B29/06 ,  C30B30/04 ,  H01L29/167 ,  H01L29/78 ,  H01L29/861

Abstract: A method of manufacturing is provided that includes providing an n-type silicon wafer, the n-type silicon wafer including n-type dopants partially compensated 20% to 80% by p-type dopants, where a net n-type doping concentration of the n-type silicon wafer is in a range from 1×1013 cm−3 to 1×1015 cm−3; forming hydrogen related donors in the n-type silicon wafer by irradiating the n-type silicon wafer with protons; and annealing the n-type silicon wafer after forming the hydrogen related donors.

公开(公告)号：US20180230622A1

公开(公告)日：2018-08-16

申请号：US15953093

申请日：2018-04-13

Applicant: Infineon Technologies AG

Inventor： Nico Caspary ,  Hans-Joachim Schulze

IPC: C30B15/04 ,  C01B33/02 ,  C30B29/06

CPC classification number: C30B15/04 ,  C01B33/02 ,  C30B29/06

Abstract: A silicon ingot has opposite ends. A specific resistance, measured along an axis between the opposite ends of the silicon ingot, has at least one point of inflection where a concavity of the specific resistance changes along the axis. According to another embodiment, a silicon ingot has a first ingot part and a second ingot part between opposite ends of the silicon ingot. The first ingot part has a different specific resistance than the second ingot part. In a region of the silicon ingot between the first and second ingot parts, the specific resistance has at least one point of inflection where a concavity of the specific resistance changes.