中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

61 records (took 0.027 seconds)

    Operating point management in multi-core architectures
    1.
    发明授权
    Operating point management in multi-core architectures 有权

    公开(公告)号：US11287871B2

    公开(公告)日：2022-03-29

    申请号：US16025955

    申请日：2018-07-02

    Applicant: Intel Corporation

    Inventor： Efraim Rotem ,  Oren Lamdan ,  Alon Naveh

    IPC: G06F1/00 ,  G06F1/3287 ,  G06F1/20 ,  G06F1/3203 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3234 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0875 ,  G06F9/30

    Abstract: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.

    Providing an interface for demotion control information in a processor
    3.
    发明授权
    Providing an interface for demotion control information in a processor 有权

    公开(公告)号：US10379596B2

    公开(公告)日：2019-08-13

    申请号：US15227040

    申请日：2016-08-03

    Applicant: Intel Corporation

    Inventor： Eliezer Weissmann ,  Nir Rosenzweig ,  Efraim Rotem ,  Yoav Ben-Raphael ,  Alon Naveh

    IPC: G06F1/3206 ,  G06F1/3287 ,  G06F1/3296

    Abstract: In one embodiment, a processor includes: a plurality of cores; a power controller including a logic to autonomously demote a first request for at least one core of the plurality of cores to enter a first low power state, to cause the at least one core to enter a second low power state, the first low power state a deeper low power state than the second low power state; and an interface to receive an input from a system software, the input including at least one demotion control parameter, where the logic is to autonomously demote the first request based at least in part on the at least one demotion control parameter. Other embodiments are described and claimed.

    Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates
    8.
    发明授权
    Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates 有权
    能量效率和节能的方法，装置和系统，包括在变化的唤醒速率下优化C状态选择

    公开(公告)号：US08996895B2

    公开(公告)日：2015-03-31

    申请号：US14317239

    申请日：2014-06-27

    Applicant: Intel Corporation

    Inventor： Alon Naveh ,  Eliezer Weissmann ,  Ofer Nathan ,  Nadav Shulman

    IPC: G06F1/00 ,  G06F1/32 ,  G06F13/24 ,  G06F15/00

    CPC classification number: G06F1/3275 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

    Abstract: A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

    Abstract translation: 处理器可以包括动态地为处理核心选择最佳C状态的电源管理技术。 对操作系统的实际工作负载的测量表现出两个重要的观察结果：（1）高中断率的突发散布在低中断速率周期和长时间的高活动水平之间; 和（2）中断率可能突然降低到当前操作系统（OS）的典型值的中断速率（例如，1毫秒）。 功率控制逻辑可以基于存储在计数器中的陈旧数据来确定C状态，而不是通过覆盖由OS或任何其它功率监视逻辑确定的C状态来确定最佳C状态。 功率控制逻辑可以动态地基于CPU空闲驻留时间和可变速率唤醒事件来确定最佳C状态以匹配预期的唤醒事件速率。

    Mechanism for saving and retrieving micro-architecture context
    10.
    发明授权
    Mechanism for saving and retrieving micro-architecture context 有权

    公开(公告)号：US11243768B2

    公开(公告)日：2022-02-08

    申请号：US16259880

    申请日：2019-01-28

    Applicant: Intel Corporation

    Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Boris Ginzburg ,  Alon Naveh ,  Nadav Shulman ,  Ronny Ronen

    IPC: G06F11/34 ,  G06F11/30 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455 ,  G06F1/3234

    Abstract: Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.

Patent Agency Ranking