公开(公告)号：US10181432B2

公开(公告)日：2019-01-15

申请号：US15461033

申请日：2017-03-16

申请人： Intel Corporation

发明人： Ameya Limaye ,  Shubhada H. Sahasrabudhe ,  Nachiket R. Raravikar

IPC分类号： H01L23/34 ,  H01L23/367 ,  H01L23/373 ,  H01L21/48 ,  H01L23/00

摘要： Embodiments of the present disclosure provide techniques and configurations for a computing system with a thermal interface having magnetic particles. In some embodiments, the computing system may include a first part, a second part, and a thermal interface to couple the first and second parts. The thermal interface may comprise a thermal interface material having magnetic particles that are aligned in a defined direction relative to a surface of the first or second part, to provide desired thermal conductivity between the first and second parts. The defined direction of alignment of magnetic particles may comprise an alignment of the particles substantially perpendicularly to the surface of the first or second part. Other embodiments may be described and/or claimed.

公开(公告)号：US20210280495A1

公开(公告)日：2021-09-09

申请号：US16328614

申请日：2016-09-29

申请人： Intel Corporation

发明人： Siddarth Kumar ,  Shubhada H. Sahasrabudhe ,  Sandeep B. Sane ,  Shalabh Tandon

IPC分类号： H01L23/40 ,  H01L23/427 ,  H01L21/48

摘要： Methods/structures of joining package structures are described. Those methods/structures may include a first side of a die disposed on a first side of a substrate, and a cooling structure on a second side of the die, wherein the cooling structure comprises a first section attached to the substrate, and a second section disposed on a second side of the die, wherein the first and second sections are separated by an opening in the cooling structure. The opening surrounds a portion of the second section, and at least one flexure beam structure connects the first and second sections.

公开(公告)号：US20170133350A1

公开(公告)日：2017-05-11

申请号：US14937022

申请日：2015-11-10

申请人： Intel Corporation

发明人： Shubhada H. Sahasrabudhe ,  Sandeep B. Sane ,  Siddarth Kumar ,  Shalabh Tandon

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/1607 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81193 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/81951 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815

摘要： Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.

公开(公告)号：US11276625B2

公开(公告)日：2022-03-15

申请号：US16328614

申请日：2016-09-29

申请人： Intel Corporation

发明人： Siddarth Kumar ,  Shubhada H. Sahasrabudhe ,  Sandeep B. Sane ,  Shalabh Tandon

IPC分类号： H01L23/367 ,  H01L23/40 ,  H01L21/48 ,  H01L23/427

摘要： Methods/structures of joining package structures are described. Those methods/structures may include a first side of a die disposed on a first side of a substrate, and a cooling structure on a second side of the die, wherein the cooling structure comprises a first section attached to the substrate, and a second section disposed on a second side of the die, wherein the first and second sections are separated by an opening in the cooling structure. The opening surrounds a portion of the second section, and at least one flexure beam structure connects the first and second sections.

公开(公告)号：US09368461B2

公开(公告)日：2016-06-14

申请号：US14280110

申请日：2014-05-16

申请人： INTEL CORPORATION

发明人： Sven Albers ,  Georg Seidemann ,  Sonja Koller ,  Stephan Stoeckl ,  Shubhada H. Sahasrabudhe ,  Sandeep B. Sane

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/05 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/141 ,  H01L2224/16238 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/0373

摘要： Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.

摘要翻译： 这里公开了与集成电路（IC）封装一起使用的接触焊盘。 在一些实施例中，本文公开的接触垫可以设置在IC封装的基板上，并且可以包括金属突出部分和金属凹部。 金属突出部和金属凹部中的每一个可以具有焊料接触表面。 金属凹部的焊接接触表面可以与金属突出部的焊接接触表面间隔开。 本文还公开了相关的设备和技术，并且可以要求保护其他实施例。

公开(公告)号：US11469185B2

公开(公告)日：2022-10-11

申请号：US16465907

申请日：2017-11-27

申请人： Intel Corporation

发明人： Je-Young Chang ,  Shubhada H. Sahasrabudhe ,  Tannaz Harirchian

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/16 ,  H01L23/04 ,  H01L25/065 ,  H01L23/42 ,  H01L23/10 ,  H01L23/40 ,  H01L23/498 ,  H01L23/367 ,  H01L23/427

摘要： Semiconductor packages having support members are provided. Support members can mitigate damage to a semiconductor die mounted on a semiconductor package. In some embodiments, an arrangement of support packages can be formed at respective locations of a frame layer that serves as a stiffener for the semiconductor package. Each support member in the arrangement can be formed from a same material of the frame layer or a different material. In some embodiments, a support member can be mounted or otherwise coupled to an exposed surface of the frame layer. In addition or in other embodiments, a support member can be mounted on a surface that supports the semiconductor die. The arrangement of support members can include support members comprising a first material and/or other support members formed from respective materials. A support member can be formed from a metal, a metal alloy, a semiconductor, a polymer, a composite material, or a porous material.

公开(公告)号：US20180269128A1

公开(公告)日：2018-09-20

申请号：US15461033

申请日：2017-03-16

申请人： Intel Corporation

发明人： Ameya Limaye ,  Shubhada H. Sahasrabudhe ,  Nachiket R. Raravikar

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/3737 ,  H01L23/42 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/27334 ,  H01L2224/29083 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/29355 ,  H01L2224/29357 ,  H01L2224/2936 ,  H01L2224/29471 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/92225 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/01062

摘要： Embodiments of the present disclosure provide techniques and configurations for a computing system with a thermal interface having magnetic particles. In some embodiments, the computing system may include a first part, a second part, and a thermal interface to couple the first and second parts. The thermal interface may comprise a thermal interface material having magnetic particles that are aligned in a defined direction relative to a surface of the first or second part, to provide desired thermal conductivity between the first and second parts. The defined direction of alignment of magnetic particles may comprise an alignment of the particles substantially perpendicularly to the surface of the first or second part. Other embodiments may be described and/or claimed.

公开(公告)号：US09953934B2

公开(公告)日：2018-04-24

申请号：US14971744

申请日：2015-12-16

申请人： Intel Corporation

发明人： Siddarth Kumar ,  Sandeep B Sane ,  Shubhada H. Sahasrabudhe ,  Shalabh Tandon

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/16

CPC分类号： H01L23/562 ,  H01L23/16 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

摘要： A warp controlled package includes a substrate that assumes a warped configuration according to the application of heat. At least one device is coupled along the substrate. A plurality of electrical contacts extend between at least the device and the substrate. One or more counter moment elements are coupled with the substrate. The one or more counter moment elements include a passive configuration and a counter moment configuration. In the counter moment configuration the one or more counter moment elements are configured to apply a counter moment to the substrate to counteract the warped configuration. In the passive configuration the one or more counter moment elements are configured to apply a neutral counter moment less than the counter moment of the counter moment configuration.

公开(公告)号：US20180190596A1

公开(公告)日：2018-07-05

申请号：US15396108

申请日：2016-12-30

申请人： Intel Corporation

发明人： Je-Young G. Chang ,  Shubhada H. Sahasrabudhe ,  Tannaz Harirchian

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/16 ,  H01L23/04 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L21/481 ,  H01L23/04 ,  H01L23/10 ,  H01L23/16 ,  H01L23/3675 ,  H01L23/4006 ,  H01L23/42 ,  H01L23/427 ,  H01L23/49816 ,  H01L23/49822 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/3511

摘要： Semiconductor packages having support members are provided. Support members can mitigate damage to a semiconductor die mounted on a semiconductor package. In some embodiments, an arrangement of support packages can be formed at respective locations of a frame layer that serves as a stiffener for the semiconductor package. Each support member in the arrangement can be formed from a same material of the frame layer or a different material. In some embodiments, a support member can be mounted or otherwise coupled to an exposed surface of the frame layer. In addition or in other embodiments, a support member can be mounted on a surface that supports the semiconductor die. The arrangement of support members can include support members comprising a first material and/or other support members formed from respective materials. A support member can be formed from a metal, a metal alloy, a semiconductor, a polymer, a composite material, or a porous material.

公开(公告)号：US09659908B1

公开(公告)日：2017-05-23

申请号：US14937022

申请日：2015-11-10

申请人： Intel Corporation

发明人： Shubhada H. Sahasrabudhe ,  Sandeep B Sane ,  Siddarth Kumar ,  Shalabh Tandon

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/1607 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81193 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/81951 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815

摘要： Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.