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公开(公告)号：US20180068887A1
公开(公告)日：2018-03-08
申请号：US15812320
申请日：2017-11-14
发明人： Mark D. Jaffe , Alvin J. Joseph , Qizhi Liu , Anthony K. Stamper
IPC分类号： H01L21/762 , H01L29/06 , H01L21/306
CPC分类号： H01L21/76289 , H01L21/02233 , H01L21/02238 , H01L21/02255 , H01L21/0273 , H01L21/26533 , H01L21/266 , H01L21/30604 , H01L21/76224 , H01L21/76283 , H01L21/76286 , H01L21/764 , H01L29/0649 , H01L29/0653 , H01L29/66651 , H01L29/66772 , H01L29/78
摘要： A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.
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公开(公告)号：US09076810B2
公开(公告)日：2015-07-07
申请号：US14508011
申请日：2014-10-07
IPC分类号： H01L21/331 , H01L29/66 , G06F17/50 , H01L21/8249 , H01L29/732 , H01L21/762 , H01L21/02 , H01L21/311 , H01L27/02
CPC分类号： H01L29/66272 , G06F17/5009 , G06F17/5036 , G06F17/5068 , G06F2217/12 , H01L21/02532 , H01L21/02595 , H01L21/31111 , H01L21/76224 , H01L21/76229 , H01L21/76232 , H01L21/8249 , H01L27/0207 , H01L29/7322 , Y02P90/265
摘要： Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.
摘要翻译： 双极晶体管结构，双极晶体管的设计和制造方法，设计具有双极晶体管的电路的方法。 设计双极晶体管的方法包括：选择双极晶体管的初始设计; 缩放双极晶体管的初始设计以产生双极晶体管的缩放设计; 基于缩放之后双极晶体管的发射极的尺寸来确定双极晶体管的缩放设计的应力补偿是否需要; 并且如果需要对双极型晶体管的缩放设计的应力补偿，则调整缩放设计的沟槽隔离布局级别相对于缩放设计的发射器布局级别的布局的布局，以产生压缩补偿的缩放设计 双极晶体管。
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公开(公告)号：US09059269B2
公开(公告)日：2015-06-16
申请号：US13738532
申请日：2013-01-10
IPC分类号： H01L21/339 , H01L23/48 , H01L27/12 , H01L29/78 , H01L29/66
CPC分类号： H01L23/34 , H01L21/84 , H01L23/3677 , H01L27/1203 , H01L29/665 , H01L29/78 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： An approach for sinking heat from a transistor is provided. A method includes forming a substrate contact extending from a first portion of a silicon-on-insulator (SOI) island to a substrate. The method also includes forming a transistor in a second portion of the SOI island. The method further includes electrically isolating the substrate contact from the transistor by doping the first portion of the SOI island.
摘要翻译： 提供了一种从晶体管吸收热量的方法。 一种方法包括形成从绝缘体上硅（SOI）岛的第一部分延伸到衬底的衬底接触。 该方法还包括在SOI岛的第二部分中形成晶体管。 该方法还包括通过掺杂SOI岛的第一部分来将衬底接触与晶体管电隔离。
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公开(公告)号：US08951896B2
公开(公告)日：2015-02-10
申请号：US13929955
申请日：2013-06-28
发明人： Alan B. Botula , Jeffrey E. Hanrahan , Mark D. Jaffe , Alvin J. Joseph , Dale W. Martin , Gerd Pfeiffer , James A. Slinkman
CPC分类号： H01L21/76251 , H01L21/04 , H01L21/265 , H01L21/26506 , H01L21/324
摘要： According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.
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公开(公告)号：US20150001622A1
公开(公告)日：2015-01-01
申请号：US13929256
申请日：2013-06-27
IPC分类号： H01L29/786 , H01L21/28
CPC分类号： H01L29/78654 , H01L21/28123 , H01L21/84 , H01L29/66613
摘要： An integrated recessed thin body field effect transistor (FET) and methods of manufacture are disclosed. The method includes recessing a portion of a semiconductor material. The method further includes forming at least one gate structure within the recessed portion of the semiconductor material.
摘要翻译： 公开了集成的凹陷薄体场效应晶体管（FET）及其制造方法。 该方法包括使半导体材料的一部分凹陷。 该方法还包括在半导体材料的凹陷部分内形成至少一个栅极结构。
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公开(公告)号：US20130130462A1
公开(公告)日：2013-05-23
申请号：US13740673
申请日：2013-01-14
发明人： David L. Harame , Alvin J. Joseph , Qizhi Liu , Ramana M. Malladi
IPC分类号： H01L29/73
CPC分类号： H01L29/73 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： Embodiments of the present invention include a method for forming a tunable semiconductor device. In one embodiment, the method comprises: forming a semiconductor substrate; patterning a first mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector; removing the first mask; patterning a second mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector; removing the second mask; and forming a single continuous collector above the second discontinuous subcollector.
摘要翻译： 本发明的实施例包括形成可调谐半导体器件的方法。 在一个实施例中，该方法包括：形成半导体衬底; 在半导体衬底上图案化第一掩模; 不受第一掩模保护的半导体衬底的掺杂区域以形成第一不连续子集电极; 去除第一个面罩; 在半导体衬底上图案化第二掩模; 所述半导体衬底的掺杂区域不被所述第二掩模保护并且在所述第一不连续子集电极的顶部上以形成第二不连续子集电极; 去除第二个掩模; 以及在第二不连续子集电极上方形成单个连续集电器。
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公开(公告)号：US10692753B2
公开(公告)日：2020-06-23
申请号：US16240304
申请日：2019-01-04
发明人： Mark D. Jaffe , Alvin J. Joseph , Qizhi Liu , Anthony K. Stamper
IPC分类号： H01L21/02 , H01L21/762 , H01L29/06 , H01L29/78 , H01L29/66 , H01L21/265 , H01L21/764 , H01L21/306 , H01L29/786 , H01L27/12 , H01L21/027 , H01L21/266
摘要： A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.
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公开(公告)号：US09847415B2
公开(公告)日：2017-12-19
申请号：US14523076
申请日：2014-10-24
发明人： Alan B. Botula , Alvin J. Joseph , Stephen E. Luce , John J. Pekarik , Yun Shi
IPC分类号： H01L29/76 , H01L29/78 , H01L29/417 , H01L29/66 , H01L29/08 , H01L29/423
CPC分类号： H01L29/7834 , H01L29/0847 , H01L29/41783 , H01L29/423 , H01L29/66575
摘要： A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.
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公开(公告)号：US09728838B2
公开(公告)日：2017-08-08
申请号：US14687002
申请日：2015-04-15
发明人： Hanyi Ding , Mark D. Jaffe , Alvin J. Joseph , Anthony K. Stamper
IPC分类号： H01L21/76 , H01L23/52 , H01Q1/22 , H01L21/762 , H01Q9/16
CPC分类号： H01Q1/2283 , H01L21/76224 , H01L23/5227 , H01Q9/16
摘要： Approaches for an on-chip antenna are provided. A method includes forming an antenna in an insulator layer at a front side of a substrate. The method also includes forming a trench in the substrate underneath the antenna. The method further includes forming a fill material in the trench. The substrate is composed of a material having a first dielectric constant. The fill material has a second dielectric constant that is less than the first dielectric constant.
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公开(公告)号：US09633894B2
公开(公告)日：2017-04-25
申请号：US14963530
申请日：2015-12-09
发明人： Mark D. Jaffe , Alvin J. Joseph , Qizhi Liu , Anthony K. Stamper
IPC分类号： H01L21/266 , H01L21/764 , H01L29/06 , H01L29/78 , H01L29/66 , H01L21/265 , H01L21/762 , H01L21/306 , H01L21/02 , H01L21/027
CPC分类号： H01L21/76289 , H01L21/02233 , H01L21/02238 , H01L21/02255 , H01L21/0273 , H01L21/26533 , H01L21/266 , H01L21/30604 , H01L21/76224 , H01L21/76283 , H01L21/76286 , H01L21/764 , H01L29/0649 , H01L29/0653 , H01L29/66651 , H01L29/66772 , H01L29/78
摘要： A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.
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