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公开(公告)号：US20240354564A1
公开(公告)日：2024-10-24
申请号：US18303968
申请日：2023-04-20
IPC分类号： G06N3/08
CPC分类号： G06N3/08
摘要： An integrated sensor array may include a semiconductor substrate. The integrated sensor array may be arranged in multiple sensor sub-arrays formed on the substrate. Each sensor sub-array may include multiple, densely packed cross-reactive sensors. Each cross-reactive sensor of within the same sensor sub-array may be functionalized differently than each of the other cross-reactive sensor of the same sensor sub-array.
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公开(公告)号：US20240202386A1
公开(公告)日：2024-06-20
申请号：US18066445
申请日：2022-12-15
IPC分类号： G06F30/20
摘要： A method, computer program, and computer system are provided for structural health monitoring. A signal corresponding to interrogation of sensors embedded within structural components associated with a structure is transmitted by a handheld or vehicle-mounted interrogator. A backscattered response signal including sensor data associated with the structure is received by the interrogator. The sensor data is compared to a threshold value corresponding to a safety factor of the structure. Maintenance or manual inspection of the structure is scheduled based on the sensor data being above the threshold value.
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公开(公告)号：US12016251B2
公开(公告)日：2024-06-18
申请号：US17445831
申请日：2021-08-25
IPC分类号： H10N52/80 , G11C11/16 , H01F10/32 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/85 , H10N52/00 , H10N52/01
CPC分类号： H10N52/80 , G11C11/161 , H01F10/3254 , H01F10/329 , H10B61/20 , H10N50/01 , H10N50/10 , H10N52/00 , H10N52/01 , G11C11/1673 , H10N50/85
摘要： Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a spin transfer torque (STT) magnetoresistive random access memory (MRAM) stack. The semiconductor structure may also include a spin orbit torque (SOT) MRAM stack vertically in series with the STT-MRAM. The SOT-MRAM stack may include a heavy metal spin hall effect rail configured to flip an SOT free-layer magnetic orientation in response to a horizontal signal through the heavy metal rail.
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公开(公告)号：US20240161408A1
公开(公告)日：2024-05-16
申请号：US18055911
申请日：2022-11-16
IPC分类号： G06T19/00
CPC分类号： G06T19/00
摘要： Embodiments of the invention are directed to a computer-implemented method that includes accessing, using a processor system, a three-dimensional (3D) model of a device-under-design (DUD). The processor system is used to receive a first design operation associated with the 3D model of the DUD. A collaboration dependency model is used to make a prediction of a dependency relationship between the first design operation and a second design operation.
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公开(公告)号：US20240094801A1
公开(公告)日：2024-03-21
申请号：US17934026
申请日：2022-09-21
CPC分类号： G06F3/011 , G16H40/63 , G06F2203/011
摘要： According to one embodiment, a method, computer system, and computer program product for biometric mixed-reality emotional modification is provided. The present invention may include collecting, by a plurality of biosensors, biometric information on a user during a mixed-reality session, wherein the biometric information comprises biomarkers; identifying, by one or more machine learning models, a mental state of the user based on the biometric information; and responsive to determining that the mental state does not match an intended emotion associated with a mixed-reality experience, modifying the mixed-reality experience with one or more virtual content elements.
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公开(公告)号：US11695004B2
公开(公告)日：2023-07-04
申请号：US17506913
申请日：2021-10-21
IPC分类号： H01L27/06 , H01L21/8249 , H01L27/082 , H01L29/66 , H01L29/78 , H01L29/732
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/0617 , H01L27/0826 , H01L29/66666 , H01L29/732 , H01L29/7827
摘要： A semiconductor device or circuit includes a vertical bipolar junction transistor (vBJT) and a vertical filed effect transistor (vFET). The vBJT collector is electrically and/or physically connected to an adjacent vFET source. For example, a vBJT collector and a vFET source may be integrated upon a same semiconductor material substrate or layer. The vFET provides negative feedback for the collector-base voltage and the vBJT emitter and collector allow for low transit times.
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7.发明授权公开(公告)号：US11683941B2
公开(公告)日：2023-06-20
申请号：US16701194
申请日：2019-12-03
CPC分类号： H10B63/34 , H10N70/066 , H10N70/24 , H10N70/821 , H10N70/841
摘要： A semiconductor structure may include two vertical transport field effect transistors comprising a top source drain, a bottom source drain, and an epitaxial channel and a resistive random access memory between the two vertical transport field effect transistors, the resistive random access memory may include an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer may contact the top source drain of the two vertical field effect transistor. The top source drain may function as the bottom electrode of the resistive random access memory. The semiconductor structure may include a shallow trench isolation between the two vertical transport field effect transistors, the shallow trench isolation may be embedded in a first spacer, a doped source, and a portion of a substrate.
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公开(公告)号：US11605673B2
公开(公告)日：2023-03-14
申请号：US17116147
申请日：2020-12-09
IPC分类号： H01L27/24 , H01L27/092 , H01L45/00
摘要： An approach to forming a semiconductor structure is provided. The semiconductor structure includes two adjacent fins on a substrate. A gate stack is on each of the two adjacent fins. The semiconductor structure includes a first source/drain on a first end of each fin of the two adjacent fins and a second source/drain on a second end of each fin of the two adjacent fins. The semiconductor structure includes a switching layer on at least the first source/drain on the first end of each fin of the two adjacent fins and a top electrode on the switching layer. A metal material over the top electrode in the semiconductor structure.
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公开(公告)号：US11594617B2
公开(公告)日：2023-02-28
申请号：US17093716
申请日：2020-11-10
IPC分类号： H01L29/66 , H01L29/423 , H01L29/78
摘要： A Vertical Reconfigurable Field Effect Transistor (VRFET) has a substrate and a vertical channel. The vertical channel is in contact with a top silicide region that forms a lower Schottky junction with the vertical channel and a top silicide region that forms an upper Schottky junction with the vertical channel. The lower silicide region and the upper silicide region each form a source/drain (S/D) of the device. A lower gate stack surrounds the vertical channel and has a lower overlap that encompasses the lower Schottky junction. An upper gate stack surrounds the vertical channel and has an upper overlap that encompasses the upper Schottky junction. The lower gate stack is electrically insulated from the upper gate stack. The lower gate stack can electrically control the lower Schottky junction (S/D). The upper gate stack can electrically control the upper Schottky junction (S/D). The control of the lower Schottky junction (S/D) is independent and separate from the control of the upper Schottky junction (S/D). The upper gate stack is stacked above the lower gate stack enabling a reduced device footprint.
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公开(公告)号：US11575023B2
公开(公告)日：2023-02-07
申请号：US17094848
申请日：2020-11-11
发明人： Clint Jason Oteri , Alexander Reznicek , Bahman Hekmatshoartabari , Jingyun Zhang , Ruilong Xie
IPC分类号： H01L29/00 , H01L29/66 , H01L29/423
摘要： A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.
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